Hacker News: 349ru3h4f03https://news.ycombinator.com/user?id=349ru3h4f03Hacker News RSShttps://hnrss.org/hnrss v2.1.1Tue, 15 Sep 2026 08:07:22 +0000<![CDATA[New comment by 349ru3h4f03 in "On Binary Translation and Its Consequences"]]>Would Rosetta 2 have worked as well for x86 APX i.e. 32 GPRs instead of 16?

(16x x86 regs fit in 32x Arm regs, whereas 32x in 32x is... much less of a fit)

]]>Sun, 13 Sep 2026 15:24:44 +0000https://news.ycombinator.com/item?id=49685044349ru3h4f03https://news.ycombinator.com/item?id=49685044https://news.ycombinator.com/item?id=49685044<![CDATA[New comment by 349ru3h4f03 in "Why is the x86 undefined instruction called ud2? Why 2?"]]>x86 has...

INT Ib INT1 INT3 INTO BOUND

]]>Sun, 13 Sep 2026 15:22:21 +0000https://news.ycombinator.com/item?id=49685012349ru3h4f03https://news.ycombinator.com/item?id=49685012https://news.ycombinator.com/item?id=49685012<![CDATA[New comment by 349ru3h4f03 in "Why is the x86 undefined instruction called ud2? Why 2?"]]>Nowadays UD0 UD1 UD2 are in the SDM and APM.

We also got UDB (D6), the one-byte variant that arrived with x86-64 for 64-bit mode.

And we have always had UDW (FF FF), aka group #5 (1st FF) with a modrm byte of mod=11b r/m=111b (/7) reg=111b (2nd FF) -- that one matters for memory with all bits set to 1, or for buses terminated to all 1 when no device claims an access.

]]>Sun, 13 Sep 2026 15:21:36 +0000https://news.ycombinator.com/item?id=49685007349ru3h4f03https://news.ycombinator.com/item?id=49685007https://news.ycombinator.com/item?id=49685007