Hacker News: CorrectHorseBat

New comment by CorrectHorseBat in "Nvidia's Risky Business"

CorrectHorseBat — Tue, 11 Aug 2026 20:42:26 +0000

Hardware companies are notoriously bad at software. The software they use sucks, the languages they use suck, the internal tooling software they write sucks.

They don't know what good developer experience is, how do you expect them to deliver it to other people?

New comment by CorrectHorseBat in "Our position on open-weights models"

CorrectHorseBat — Tue, 28 Jul 2026 06:02:05 +0000

>Schrödinger's China at once is an evil entity looking to use AI for their own nefarious purposes yet also willing to cooperate with their main competitor to prevent other actors (who??) from achieving similar goals (all while under a chip embargo too!!)

I don't see the contradiction, even if China is evil, why would they want others to be able to do the same thing?

The USA and USSR also signed the Partial Nuclear Test Ban Treaty during the height of the cold war.

New comment by CorrectHorseBat in "If digital computers are conscious, they are conscious at the hardware level"

CorrectHorseBat — Mon, 27 Jul 2026 12:50:25 +0000

There's also information in the compiler and the zip binary, without that I'm pretty sure it's not possible.

New comment by CorrectHorseBat in "Making Xen's dom0 I/O path NUMA aware"

CorrectHorseBat — Fri, 24 Jul 2026 18:02:17 +0000

KVM has a much larger attack surface than Xen

New comment by CorrectHorseBat in "Kimi K3, and what we can still learn from the pelican benchmark"

CorrectHorseBat — Fri, 17 Jul 2026 19:53:45 +0000

Chinese is also written left to right

New comment by CorrectHorseBat in "Using precision editing to study human embryo development shows master gene"

CorrectHorseBat — Tue, 07 Jul 2026 06:49:51 +0000

If you prefer the term person to avoid confusion, fine by me. But then also don't use the term "experimenting on humans", because the meaning of that is experimenting on persons against their will.

There is nothing extra magical about conception that makes the creation of a human (or a person if you prefer that), all of the DNA already existed before and nothing that defines a person is yet present.

New comment by CorrectHorseBat in "Using precision editing to study human embryo development shows master gene"

CorrectHorseBat — Mon, 06 Jul 2026 22:19:57 +0000

Testing on early stage embryos is a thing yes. They have no brain, no heartbeat, feel no pain. Yes, they could potentially develop into a human being, but I wouldn't call it a live human yet. I understand your repulsion, but to other people it's no different than testing on sperm, eggs or other human tissues. And as the other guy said, these were discarded embryos from IVF, they would never become humans.

New comment by CorrectHorseBat in "Google Hits 50% IPv6"

CorrectHorseBat — Sun, 21 Jun 2026 11:05:11 +0000

Here in Belgium it's the other way around. we've had IPv6 for over 10 years for basically all home internet, but mobile is still ipv4 only. Not sure why since it's all the same companies.

New comment by CorrectHorseBat in "US battery manufacturing output continues to break records"

CorrectHorseBat — Mon, 15 Jun 2026 21:46:28 +0000

No Korea and Japan? Aren't most of the big non-Chinese battery companies Korean and Japanese?

New comment by CorrectHorseBat in "Adafruit Receives Demand Letter from Fenwick Legal Counsel on Behalf of Flux.ai"

CorrectHorseBat — Tue, 02 Jun 2026 14:08:20 +0000

It is far from solved in IC, synthesis tools sometimes still do really stupid things and there's still quite a lot of hand-holding required to get to a working chip.

New comment by CorrectHorseBat in "I believe there are entire companies right now under AI psychosis"

CorrectHorseBat — Sat, 16 May 2026 18:17:26 +0000

I can't imagine humanity, let alone any company or the stock market survive runaway AI.

New comment by CorrectHorseBat in "If America's so rich, how'd it get so sad?"

CorrectHorseBat — Thu, 23 Apr 2026 16:27:00 +0000

Median doesn't say anything about the extremes and income isn't wealth.

New comment by CorrectHorseBat in "Škoda DuoBell: A bicycle bell that penetrates noise-cancelling headphones"

CorrectHorseBat — Thu, 09 Apr 2026 10:50:37 +0000

Bicycle bells can be used to warn other cyclists

New comment by CorrectHorseBat in "VHDL's Crown Jewel"

CorrectHorseBat — Mon, 30 Mar 2026 19:34:04 +0000

Real hardware has clock trees. Wouldn't all (most?) problems with delta cycles go away if the HDL understood the concept of clocks and clock balancing?

New comment by CorrectHorseBat in "VHDL's Crown Jewel"

CorrectHorseBat — Mon, 30 Mar 2026 19:28:44 +0000

In a way is further away, but in another way it's actually closer to how real hardware works: Clock (and reset) trees are real physical things which exist on all digital chips.

New comment by CorrectHorseBat in "VHDL's Crown Jewel"

CorrectHorseBat — Mon, 30 Mar 2026 18:56:53 +0000

Is it really if you restrict yourself to sensible design practices? You generally want to simulate simple clocked Logic with a predefined clock, most of the time anything else is a mistake or bad design. So just if rising edge clk next_state <= fn(previous_state, input) . It seems to me VHDL and verilog are simply at the wrong abstraction level and by that they make simulation needlessly complicated and design easy to do wrong. To me it seems that if they had the concept of clocks instead none of this would be necessary and many bugs avoided (but I'm no expert on simulator design, so I might be missing something...)

New comment by CorrectHorseBat in "VHDL's Crown Jewel"

CorrectHorseBat — Mon, 30 Mar 2026 17:16:49 +0000

I'm not sure if you are trolling. 99.999% of digital design is "if rising edge clk new_state <= fn(old_state, input)", with an (a)sync reset. The language should make that the default and simple to do, and anything else out of the ordinary hard. Now it's more the other way around.

New comment by CorrectHorseBat in "VHDL's Crown Jewel"

CorrectHorseBat — Mon, 30 Mar 2026 09:08:02 +0000

Those are analog circuits, if you put them in your digital design you are doing something wrong.

New comment by CorrectHorseBat in "VHDL's Crown Jewel"

CorrectHorseBat — Mon, 30 Mar 2026 06:57:06 +0000

The real question is, why do we even need this? Why don't VHDL and Verilog just simulate what hardware does? Real hardware doesn't have any delta cycles or determinism issues due to scheduling. Same thing with sensitivity lists (yes we have */all now so that's basically solved), but why design it so that it's easy to shoot in your own foot?

New comment by CorrectHorseBat in "Why I forked httpx"

CorrectHorseBat — Wed, 25 Mar 2026 09:49:47 +0000

Don't you need to register and actively defend you trademark for it to apply?