Hacker News: Taniwha

New comment by Taniwha in "Can you reverse engineer an ASIC?"

Taniwha — Fri, 07 Aug 2026 05:59:24 +0000

You might is they included DFT (design for test, stuff to make sure when you make a chip all of it actually works) - a scan chain thru all the internal flops will provide you with info about the internal flops and how they are connected - reverse engineering this into a model of reality would certainly be extremely hard, but maybe not impossible

New comment by Taniwha in "Can you reverse engineer an ASIC?"

Taniwha — Fri, 07 Aug 2026 00:31:19 +0000

In fact if you have the sky130 libraries installed (it's where I'm working) you can get a spice netlist out of it in about 10 seconds - really they should have flattened it

New comment by Taniwha in "Can you reverse engineer an ASIC?"

Taniwha — Fri, 07 Aug 2026 00:26:16 +0000

I take it back, it's a sky130 .gds the gates are explicitly in there

New comment by Taniwha in "Can you reverse engineer an ASIC?"

Taniwha — Fri, 07 Aug 2026 00:23:03 +0000

I'm a chip designer, back in the early 90s I visited a small silicon house who were doing some work for us, their boardroom table had been taken over by a giant sized photomicrograph of IBM's VGA chip and they had a bunch of summer hire grad students tracing wiring and matching standard cells (easier back then because we only worked in 2 layers of metal).

They weren't trying to steal IBM's design, they already had one of their own, what they wanted to know was "is there any as yet unannounced functionality in the IBM VGA chip?" they didn't want to be caught out when some unknown registers popped up. Of course it turned out there was as yet unannounced functionality - but not by IBM's design, more because of the orthogonality of the design - MODE-X was discovered and became the basis for DOOM's speed, anyone who didn't support it lost out

New comment by Taniwha in "Can you reverse engineer an ASIC?"

Taniwha — Fri, 07 Aug 2026 00:16:48 +0000

yes, but at the transistor level .... it has no idea at that level how those transistors are arranged into gates directly

New comment by Taniwha in "Can you reverse engineer an ASIC?"

Taniwha — Fri, 07 Aug 2026 00:14:50 +0000

It's even easier in this case because they've included the original verilog source ....

New comment by Taniwha in "The Silicon Valley Founder Meat Grinder"

Taniwha — Sat, 01 Aug 2026 22:19:12 +0000

I think the real watershed wan't bitcoin, it was the internet bubble, before that the rule of thumb was you couldn't go public without 5 consecutive quarters of profit - you really had to build something real - suddenly you could do it on hype alone and the focus turned to that

New comment by Taniwha in "Truth is not a direction: a Tarski attack on LLM probes"

Taniwha — Wed, 29 Jul 2026 11:43:38 +0000

Yes exactly, sure they need to know about "Pride and Prejudice" but they have no way to tell it didn't happen, nor any way to tell that all people of that age lived that way (most were dirt poor scrabbling for a living)

New comment by Taniwha in "Truth is not a direction: a Tarski attack on LLM probes"

Taniwha — Wed, 29 Jul 2026 08:22:48 +0000

I think that one of the main problems with LLMs is that we're shoveling everything in to them, without any guidance as to what is "real"/"true"/"factual" - crazy anti-vaxxer-cooker stuff is is sitting in their along with science without any concept of scientific reality and no guidance to what is real and what is insane minds spinning on each other

New comment by Taniwha in "Hooray for the Sockets Interface"

Taniwha — Wed, 29 Jul 2026 03:12:21 +0000

The article kind of misses out on the networking standards of the time - there were many of which TCP and IP were just one, most of the rest were either proprietary (DNA SNA BNA etc) and incompatible, or owned by telecoms who wanted to be able to charge per packet(X.25).

TCP/IP won (IMHO) because the implementation was open source, and because no one was going to make a buck by locking others out (or charging them for the right to build an implementation). Plus there was a working reference implementation available for the taking

New comment by Taniwha in "Designing an Ethernet Switch ASIC"

Taniwha — Sat, 25 Jul 2026 01:20:17 +0000

On TinyTapeout you can add more tiles up to 16 times the size of this (at which point you likely jump to waferspace)

New comment by Taniwha in "The Computer at the Bottom of a Canal"

Taniwha — Sat, 18 Jul 2026 23:24:55 +0000

I'm in 2 minds, I'm strongly in the RISC camp these days, I know how hard it is to build a truly performant CPU and think that simpler is better as far as ISAs go. Adding segmentation hardware into the addressing path means more clocks and makes it's harder to detect loads/stores that interfere with each other (all load/stores have to block each other until the addressing/tlb lookup has been done ie detecting aliasing ).

A true capability architecture needs separate register files for pointers and data with protections enforced when the address registers are loaded/stored, it's a step away from our models of linear address spaces that many of the languages we use today are based on. And any new CPU that requires everyone to learn a new language is probably a non-starter as a mainstream CPU

New comment by Taniwha in "The Computer at the Bottom of a Canal"

Taniwha — Sat, 18 Jul 2026 23:18:33 +0000

It was more than 40 years ago, before I had the skills to build chips, I'm afraid I've kept nothing of that design

New comment by Taniwha in "The Computer at the Bottom of a Canal"

Taniwha — Sat, 18 Jul 2026 12:35:57 +0000

Thing is capability machines (like this and the 432 and lots of research machines) were very much the thing at the time - cutting edge even. The research literature was full of them. I did a paper design at the time.

What ate them up was "what can you fit all on a chip with not many pins", followed by "what can you fit along with a cache on a chip with more pins", things move so much faster if everything's on the same die.

Tagged architectures are old, Burroughs mainframes had them back in the 70s along with rudimentary hardware objects (pageable even)

New comment by Taniwha in "Starlink from 1984"

Taniwha — Fri, 17 Jul 2026 10:37:59 +0000

StarLAN was a 1Mb twisted pair networking system that was pre twisted pair ethernet

New comment by Taniwha in "Sam Neill has died"

Taniwha — Mon, 13 Jul 2026 10:03:47 +0000

Pretty sure it's "But I LOVE what he did for the Australian flag." - he is a kiwi but that's arguably the Aussie flag with the colonial bit replaced with the local one

New comment by Taniwha in "Jellyfish Undersea Roundabout"

Taniwha — Sun, 12 Jul 2026 10:14:37 +0000

Like Greenland,the Faroe Islands are a self-governing, autonomous territory within the Kingdom of Denmark. I'm sure this is highway funding from the mainland.

New comment by Taniwha in "Digital Deli, 1984 book by early PC hackers and enthusiasts"

Taniwha — Sat, 11 Jul 2026 23:46:31 +0000

In context, around 1980 we bought 1.5MB of memory (core, real core, hand threaded core) for our Burroughs mainframe, we paid more than $1M (1980s) dollars for it. With 3MB our 1MHz mainframe supported 40 users.

You make do with the memory and cycles available, things get easier as the resources get less tight, it's easy to use things like garbage collection rather than doing the hard yards and managing memory yourself, or to break branch prediction by using virtual objects

New comment by Taniwha in "Book: RISC-V System-on-Chip Design"

Taniwha — Sat, 11 Jul 2026 22:29:26 +0000

You don't really fetch 66 bytes instead of 64, what real implementations do is read cache lines (of whatever size) and hold on to 2 bytes from the previous cache line if there was 1/2 a 32-bit instruction at the end of the previous cache line (the ISA has the 16/32-bit tag in the lower byte so you know how big an instruction will be even if you've only seen half of it)

New comment by Taniwha in "Installing A/UX 1.1 like it's the 90s"

Taniwha — Tue, 07 Jul 2026 02:06:25 +0000

It's possible that later A/UXs required booting MacOS - but when we started we got 1/2 the initial prototype production run of Mac 2s (no cases, bugs in pals, probably no standard ROMs yet)

Our standard agreement for porting Unix to new hardware (we did something like 150 different boxes, not just macs) required a minimal ROM monitor that could download code from a serial port (we could provide source), we'd take it from there, write S/A code to store data on the harddrive, download a file system, start downloading kernels into ram debugging the disk and serial drivers until we got a shell prompt ... then moving development onto the box