It is also true that COVID can weaken your general immune system.

But that doesn’t mean that getting COVID won’t increase your immunity against a future COVID infection, temporarily at least, just the way the effectiveness of the vaccine is temporary.

OpenAI commented on the verboseness of answers as something they need to work on.

I don’t get the “it’s not a service” argument. It’s not relevant. There’s no ongoing cost with many software licenses either. It’s just a business model.

For my personal case, it still doesn’t matter, of course.

It’s not a subscription, but the idea is the same.

It doesn’t bother me one bit: I bought the car knowing full well that it wasn’t included, I don’t need it (the standard acceleration is already more than I ever had before), end of story.

Car engines have been under the control of software for decades now, with different products differing by the program. The only difference here is that there’s now the option to change the program over the air.

Nobody would have complained if Mercedes had offered 2 versions without the option to upgrade.

https://www.youtube.com/watch?v=_AoCK5r2TWg

Even the numbers of PCIe bandwidth test might not change much, even it's trying to test medium size memory to memory block transfers.

When I look at my daily home computer usage, it’s remarkable how little I calculate on my local computer that’s actually with protecting.

Just yesterday, I bought an extra 64GB for my home Linux PC. I absolutely couldn’t care less about it crashing or calculating the wrong result every blue moon (in practice: never), but I did choose the RAM sticks that were $10 cheaper.

Today’s iGPUs are fast enough comfortable run plenty of games.

I have work provided high-end POS Dell Precision engineering laptop. It has an Nvidia discrete GPU, but I don’t think I’ve ever actually needed its power, and I’d gladly trade it for a laptop without…

In fact, the 4000 series still has PCIe 4.

Moving data around for a GPU is about feeding the shader cores by the memory system. PCIe is way too slow to make that happen. That’s why a GPU has gigabytes of local RAM.

We're not talking here about the latency that gamers care about, the one that's measured in milliseconds.

I've never seen any literature that complained about load/store access latency in the shader core. It's just so low level...

It’s true tbat GA102 has double the FP32 units, but the way they works is very similar to the way SMs have 2x FP16 in that you need to go out of your way to benefit front them. Benchmark show this as well.

I like to think that Nvidia’s SM version nomenclature is a pretty good hint, but I guess it just boils down to personal opinion about what constitutes a base architecture.

The weird part is that this latency difference has to be due to a terrible MC design by AMD, because there's not a huge difference in latency between any of the current DRAM technologies: the interface between HBM and GDDR (and regular DDR) is different, but the underlying method of accessing the data is similar enough for the access latency to be very similar as well.

Turing is an evolution of Volta. In fact, in the CUDA slides of Turing, they mention explicitly that Turing shaders are binary compatible with Volta, and that's very clear from the whitepapers as well.

Ampere A100 and Ampere GeForce have the same core architecture as well.

The only differences are in HPC features (MIG, ECC), FP64, the beefiness of the tensor cores, and the lack of RTX cores on HPC units.

The jury is still out on Hopper vs Lovelace. Today's presentation definitely points to a similar difference as between A100 and Ampere GeForce.

It's more: the architectures are the same with some minor differences.

You can also see this with the SM feature levels:

Volta: SM 70, Turing SM 75

Ampere: SM 80 (A100) and SM 86 (GeForce)

But what kind of latency are we talking about here?

CDNA has 16-wide SIMD units that retires 1 64-wide warp instruction every 4 clock cycles.

RDNA has a 32-wide SIMD unit that retires 1 32-wide warp every clock cycle. (It's uncanny how similar it to to Nvidia's Maxwell and Pascal architecture.)

Your 1/4 number makes me think that you're talking about a latency that has nothing to do with reads from memory, but with the rate at which instructions are retired? Or does it have to with the depth of the instruction pipeline? As long as there's sufficient occupancy, a latency difference of a few clock cycles shouldn't mean anything in the context of a thousand clock cycle latency for accessing DRAM?