A year ago I bought a 14 dot something FreeBSD installation DVD for i386 and x86_64 that also came with a source code DVD for many packages (which I lost unfortunately) from the FreeBSDMall website which has been down for a while so I couldn't order a replacement.

Bruh, I am not "gaming the system", the CIA (Central Intelligence Agency) is gaming the system.

It's not like they called you a slur. Just because two States are fighting doesn't mean that a Ukrainian civilian living in Ukraine has to beat up a Russian civilian living in Ukraine because they can't pronounce a Ukrainian word.

I am also Ukrainian, but I do not want my ethnicity to be known for petty violence.

Social Media would sooner show someone a video about how The War of the Bucket was necessary (https://en.wikipedia.org/wiki/War_of_the_Bucket) than say the history of the fine arts.

This is because petty content gets users to stay on sites longer despite the users feeling as though something is wrong but they can't identify it, so they keep using the sites.

For example: I want to speak with real people and see meaningful content, not bots waiting to mention that I made a typo, therefore I'm wrong, just to get users to stay on sites longer.

I am also ashamed of Ukrainians beating up Russians who live in Ukraine all because they can't pronounce the word "Паляниця", meaning strawberry in Ukrainian.

It's not like they called you a slur, no, its all because they can't pronounce the word "strawberry" in Ukrainian. Gosh, the pettiness.

I am also Ukrainian, but I do not support violence, especially violence caused by pettiness.

Comments URL: https://news.ycombinator.com/item?id=48960716

Points: 3

# Comments: 2

We are planning on adding our Vita Programming Language Frontend, Intermediate Representation Optimizations, a Vita Intermediate Representation if deemed necessary, and a backend for the Vita FPGA Architecture to our fork of LLVM's circt project. Mainlining our patches is welcome.

We are also evaluating any useful fully open source hardware description language compilers that exist, but are missing one or more fully open source FPGA backends so that we can add our Vita FPGA Architecture backend.

The word "Vita" is a generic latin word meaning "life". My name is Vitalii Skikun, so I can't be sued for using part of my name to name stuff. (See how a man named Sattar Buksh in Pakistan won a lawsuit initiated by Starbucks Corporation: https://food.ndtv.com/news/starbucks-versus-sattar-buksh-story-of-the-fascinating-dispute-that-went-on-for-years-9257901)

"VitaOS" is a revoked USPTO trademark and Sony Corporation was refused the trademark of the word "Vita" in the European Union and no one owns the trademark for the word "Vita" in the United States because they can't.

So you companies better not sue me over the word "Vita", cause if you do, I'll win in court.

Edit: I forgot to mention that I'm not gonna use Yosys and NextPNR because they are reverse engineering efforts, and that is a unwelcome gray area legal territory for us to be in.

My code is at https://github.com/VitaSetLLC/VitaOS-Livre

Comments URL: https://news.ycombinator.com/item?id=48944209

Points: 1

# Comments: 0

1. Proposal Description:

  The Vita FPGA Architecture Subproject is licensed under The VitaSet License.

  The VitaSet License is a permissive license which does not offer any implied warranties and patent grants and does not require the inclusion of this license's text on binary and hardware forms of the source code that is licensed under this license.

  This is to prevent executables and computer chips from wasting resources on including license text, but for source code to keep copyright attribution, so that when source code access gets interrupted, no claim of copyright infringement can be made towards the developers, as the claimant would have the copyright header of this license.

  The Vita FPGA Architecture Verilog files VitaFPGAArchLogicBlock.v and VitaFPGAArchMemoryBlock.v are bugfree.

  Any Vita FPGA Architecture Logic Block can act as though it is an Vita FPGA Architecture Interconnect Block. Thus, any possible truth-table can be expressed with enough Vita FPGA Architecture Logic Blocks, Vita FPGA Architecture Interconnect Blocks and Vita FPGA Architecture Memory Blocks. Thus, any integrated circuit could run on the Vita FPGA Architecture, given enough Vita FPGA Architecture Logic Blocks, Vita FPGA Architecture Interconnect Blocks and Vita FPGA Architecture Memory Blocks are available.

  Vita FPGA Architecture Chip and Toolchain Investment Proposition

  I am the Founder and CEO of VitaSet LLC.

  Over $400 have been donated by my relatives to me during late 2023. No other funds have been raised.

  https://github.com/efabless/clear - The Open Source FPGA ASIC. A open source Apache 2.0 eFPGA + VexRiscV CPU Chip that only sold a couple hundred physical computer chips before they stopped selling anymore through Tiny-Tapeout. I did not read their source code, my Vita FPGA Architecture was designed exclusively by me entirely from scratch. I have however read the GitHub Issues of the Clear FPGA Project and I see someone asking about the bugginess of the reset circuitry. My Vita FPGA Architecture is bug-free and permissively licensed under an open source license.

  Reducing the environmental waste caused by upgrading computer hardware, as simple software updates can be issued to update the FPGA Bitstreams instead of manufacturing new physical computer chips.

  Also, people can take advantage of the Vita FPGA Architecture to code up and use Hardware Accelerated Programs when computer chip transistors stop getting smaller.

  The Vita FPGA Architecture is synchronous clocked logic with an synchronous reset, so unlike the incompatibility of asynchronous integrated circuits, it will be compatible with the synchronous clocked ecosystem of commercial integrated circuits.

  https://github.com/VitaSetLLC/VitaSet-LLC-Asymmetric-Cryptographic-Public-Key

Also the Vita FPGA Architecture Logic and Memory Blocks are bug-free.

Using two input, one output nand or two input, one output nor gates, one can express any possible truth table.

The VitaFPGAArchMemoryBlock.v file implements a D-Flip Flop with two configurable inputs and two configurable outputs that output the same value in two directions.

The VitaFPGAArchLogicBlock.v file implements a LUT2 with two configurable inputs and two outputs outputting one bit in two directions.

A LUT2 can be programmed to ignore one or both inputs.

Thus, any possible truth table can be expressed with enough Vita FPGA Architecture Logic Blocks.

Comments URL: https://news.ycombinator.com/item?id=48226018

Points: 2

# Comments: 1