https://www.gnu.org/licenses/license-list.html#FreeBSD

I was responding to this line, which I feel marginalises intersex people and could have been more inclusively worded.

I apologise if my comment somehow seemed to defend LLMs having a biological sex, despite me having said nothing to that effect.

The chart in [1] is a good visualisation of that, if you wish to learn more.

[1]: https://www.scientificamerican.com/article/beyond-xx-and-xy-...

Nothing forces you to use C++ scripting here; Yosys has a shell that you can enter commands in, and it takes via `-s` a file of commands; a script.

That the default scripts are written in C++ to not need dependencies does not mean you also need to write your scripts in C++.

Yes, those flows use ScriptPass, because for the most part they are scripts. If they were written in Tcl, then Yosys would need to depend on a Tcl interpreter, and equivalently a Python interpreter for Python. By just using C++ for these scripts which usually only developers need to modify, Yosys does not need to depend on either.

But anyway, if I was going to mess about with the flow that much, I'd start by running `help synth_xilinx`, which outputs a list of all the commands that it calls (more or less; it can't model control flow like a proper language can), and then that can be edited into what I need it to do.

Obviously it'd be off-topic to try to discuss your particular needs and use-cases of Yosys here, so feel free to email me at lofty@yosyshq.com.

> let me take this opportunity to ask a question about something that makes absolutely zero sense to me: why did yosys insist on sticking with tcl over some more modern/well-known/familiar scripting language? yes everyone has their favorite tcl scripts for vivado or intel or whatever but none of them are transferrable to yosys irrespective of that fact that yosys supports tcl.

First: PYosys exists as Python bindings for Yosys, so you can in fact use a more modern scripting language for this.

Second: even if the Tcl scripts are not transferrable, a lot of our users do still have Tcl experience, and that transfers if nothing else.

But personally? For a lot of tasks you don't need a scripting language. If you want to turn a set of Verilog files into a JSON to pass to nextpnr-ecp5, that's `yosys -p "synth_ecp5 -abc9 -top top -json design.json" *.v` and there is neither Tcl nor Python involved here.

> further more, why is yosys itself basically scripting of ABC and nextpnr and etc using cpp instead of again using just some reasonable scripting language to connect the pieces?

Yosys is not simply some scripting around ABC: you need to parse input files, store this in an intermediate representation (RTLIL), elaborate and monomorphise the input structure, perform optimisation and logic minimisation on it; you need to map large structures like memories, hard multipliers and carry chains (ABC can't do that), legalise flop types and only then can you pass the logic to ABC. Once you get that logic from ABC, you need to turn it into cells that tooling recognises.

That the "script passes" we have that most front-end users use are so simple is because the complex logic is packed into neat passes to call.

> > multi-electrostatic placer

> um why? dreamplace exists? https://github.com/limbo018/DREAMPlace

We're aware of DREAMPlace, however: DREAMPlace itself is for ASIC applications, so you'd want to use DREAMPlaceFPGA instead, which is...limited to a simplified Xilinx architecture or whatever partial FPGA Interchange Format support they have. We consider speed a feature, and having to deserialise the target device and netlist into FPGA Interchange Format in the hopes that DREAMPlaceFPGA can understand it is...not fast.

So instead we're working on our own multi-electrostatic placer which can more tightly integrate with nextpnr than something using DREAMPlace[FPGA] could.

(actually nextpnr has slowly-maturing support for Lattice MachXO{2,3}, Intel Cyclone V and Gowin parts too)

to be blunt: nextpnr is what happens when you look at VPR as prior art and base every design decision around doing the opposite of VPR.

VPR is flexible, true: you can define an architecture description inside an XML file, but I view the VPR XML format to be poorly considered.

- commonly in an FPGA you will have "legality constraints" - for example, a block of LUTs cannot simultaneously be in carry-chain mode and act as LUT RAM. to produce a legal solution, all these constraints must be satisfied. to nextpnr this is [two basic](https://github.com/YosysHQ/nextpnr/blob/master/docs/archapi....) [API calls](https://github.com/YosysHQ/nextpnr/blob/master/docs/archapi....). to vpr, you must [walk the architecture](https://github.com/verilog-to-routing/vtr-verilog-to-routing...) to discover and cache legal placement positions. - VPR often requires significantly more detail about an FPGA than is easy to provide; for example, [how switchboxes are laid out](https://docs.verilogtorouting.org/en/latest/arch/reference/#...), or [routing metal resistance/capacitance](https://docs.verilogtorouting.org/en/latest/arch/reference/#...). to nextpnr, routing is just nodes and edges on a graph.

Further, VPR's algorithms tend not to be designed with performance in mind; simulated annealing as a placement method does not scale well past the tens of thousands of LUTs, which is why nextpnr moved from full simulated annealing to [heterogenous analytic placement](https://ieeexplore.ieee.org/document/6339278), and recently we have been working on a [multi-electrostatic placer](https://dl.acm.org/doi/abs/10.1145/3489517.3530568); both significantly more scalable methods based on using mathematical optimisation methods to place things nearby.

[1]: https://twitter.com/workingjubilee

Additionally, I'd like to clarify that nMigen generates Verilog indirectly; it actually generates RTLIL, which is the intermediate representation of Yosys, and then Yosys turns it into Verilog after some cleanup passes.

I'll happily admit to being biased, but nMigen is so much easier for me to work in than Verilog ever was.

The PS3 does not have self-modifying PPC code (SCEI forbade it), which means the PPE blob can be compiled ahead-of-time (RPCS3 converts it into LLVM). The SPE data can self-modify, however, but (to my knowledge) does not require extensive synchronisation, therefore each SPE core can be put on a thread.

The PS2 code has fairly extensive use of self-modifying code; Naughty Dog in particular will frequently load parts of the executable in and out of memory on both the PS2 main processor (the EE) and the PS1 processor (the IOP), and rely on the synchronisation between these two separate processors to be fairly tight. Trying to make the EE and IOP separate threads running simultaneously breaks this synchronisation, so the EE and IOP have to run on the same thread.

Additionally, the PS2 has two vector units; VU0 is associated with the EE (it can be used as a floating-point SIMD unit in the EE instruction stream) and VU1 is associated with the GS [the PS2's GPU, the Graphics Synthesizer] Interface (GIF) (it can directly output primitives to the GS). This means that VU0 needs to run on the same thread that the EE runs on (because there is instruction stream interlocking), and VU1 needs relatively tight synchronisation to the GS (it is feasible to put it on its own thread, but games can be quite picky with timings)

Symbiotic EDA comes to mind. However, I would argue they don't need to be great, just good.

I don't have a copy of Vivado to hand (I have an Altera dev board instead), but I can take PicoSoC with Yosys/nextpnr and have a bitstream in about a minute. If I try the same task in Quartus, that takes about five minutes. Producing a (relatively) inefficient bitstream actually speeds up the compile/run cycle in that scenario.

If the design meets timing, which is often decided by external factors, any extra time spend trying to make the design "better" is wasted time.

As for a "more traditional computing" experience, you can always look for an SGI.

RISC-V borrows heavily from MIPS, so the two have a pretty similar development experience.

[1]: https://github.com/frno7/linux or else source the official PS2 Linux Kit.