Hacker News: acutelittlebox

New comment by acutelittlebox in "A 3rd World Embedded Engineer Responds to "RISC-V They Should Have Known Better""

acutelittlebox — Mon, 17 Aug 2026 02:10:35 +0000

no, i'm talking about the core designs, not finished CPUs you could buy. using a leading-edge node is prohibitively expensive so nearly everything RISC-V i've seen has been using around 22nm to 12nm nodes. if you had an example of any of those cores in a finished product on a similar node they should be competitive, and in the meantime once people can get their hands on them you could test them against each other at low clock speeds to see how they compare.

New comment by acutelittlebox in "A 3rd World Embedded Engineer Responds to "RISC-V They Should Have Known Better""

acutelittlebox — Mon, 17 Aug 2026 01:00:58 +0000

from my understanding there's the SiFive P870, Tenstorrent Ascalon X, and Condor Computing Cuzco among others

New comment by acutelittlebox in "A 3rd World Embedded Engineer Responds to "RISC-V They Should Have Known Better""

acutelittlebox — Sun, 16 Aug 2026 23:15:58 +0000

the author just focused on his personal experiences regarding RISC-V and what he's been able to see himself as an embedded developer. there's already RISC-V SBCs that are on par with the Raspberry Pi 5 and in terms of IPC the best RISC-V cores are only lagging 5 years or less behind the best x86 and ARM cores.

New comment by acutelittlebox in "A 3rd World Embedded Engineer Responds to "RISC-V They Should Have Known Better""

acutelittlebox — Sun, 16 Aug 2026 22:43:39 +0000

the current highest performance RISC-V systems you can buy off a shelf are equivalent to a raspberry pi 5 so they're not terribly behind. in terms of IPC, currently available RISC-V cores are already basically on par with Zen 3 and Apple M1 from what i understand and Jim Keller believes that RISC-V will be the one that leads the way for raw performance.

New comment by acutelittlebox in "RISC-V: They Should Have Known Better"

acutelittlebox — Sat, 15 Aug 2026 08:10:23 +0000

I feel like that's largely mitigated by profiles. RVA23 is really looking like it'll be the modern base target used for high performance application processors and it makes mandatory pretty much everything you'd want for those use cases, and other comments by people familiar with designing RISC-V CPUs mention that the variable length encoding can be dealt with in a very simple manner that doesn't even add another pipeline stage so it doesn't seem like it's all that big of a deal while also bringing in benefits in code size reduction. Not everyone is adopting it, but several major players have set the stage by mandating it.