Hacker News: clausecker

New comment by clausecker in "A SIMD coding challenge: First non-space character after newline"

clausecker — Tue, 30 Dec 2025 01:48:22 +0000

You can find the first set bit in an integer with a machine instruction, it's completely branch free. gcc has __builtin_ctz() for this. You'll either need to iterate over all set bits (so one branch per set bit) or use a compression instruction (requiring AVX-512) to turn the bit set into a set of integers.

That said, as you seem to actually want to do something with the results, you'll take a branch per match anyway, so I don't see the problem.

Hacking Washing Machines [video]

clausecker — Tue, 30 Dec 2025 01:40:49 +0000

Article URL: https://media.ccc.de/v/39c3-hacking-washing-machines

Comments URL: https://news.ycombinator.com/item?id=46428496

Points: 222

# Comments: 49

New comment by clausecker in "A SIMD coding challenge: First non-space character after newline"

clausecker — Sun, 28 Dec 2025 18:24:51 +0000

So I've thought about it and I don't really feel like spending more time to convince you that this works. If you have questions I am happy to answer them, but please write your own code.

New comment by clausecker in "A SIMD coding challenge: First non-space character after newline"

clausecker — Sun, 28 Dec 2025 18:23:28 +0000

This does track the state. If you want to track it across multple vectors of input, you'll need to carry it over manually.

New comment by clausecker in "A SIMD coding challenge: First non-space character after newline"

clausecker — Fri, 26 Dec 2025 00:24:55 +0000

You can do it like this, assuming A is the mask of newlines and B is the mask of non-spaces.

1. Compute M1 = ~A & ~B, which is the mask of all spaces that are not newlines 2. Compute M2 = M1 + (A << 1) + 1, which is the first non-space or newline after each newline and then additional bits behind each such newline. 3. Compute M3 = M2 & ~M1, which removes the junk bits, leaving only the first match in each section

Here is what it looks like:

    10010000 = A
    01100110 = B
    00001001 = M1 = ~A & ~B
    00101010 = M2 = M1 + (A << 1) + 1
    00100010 = M3 = M2 & ~M1

Note that this code treats newlines as non-spaces, meaning if a line comprises only spaces, the terminating NL character is returned. You can have it treat newlines as spaces (meaning a line of all spaces is not a match) by computing M4 = M3 & ~A.

New comment by clausecker in "Package managers keep using Git as a database, it never works out"

clausecker — Fri, 26 Dec 2025 00:01:53 +0000

We do this with FreeBSD ports, but users don't have to clone the ports tree unless they want to modify ports or compile them with custom options.

New comment by clausecker in "Uninitialized garbage on ia64 can be deadly (2004)"

clausecker — Mon, 08 Dec 2025 13:50:44 +0000

And the same reason NVRAM was dead on arrival. No affordable dev systems meant that only enterprise software supported it.

New comment by clausecker in "Addressing the adding situation"

clausecker — Wed, 03 Dec 2025 12:40:11 +0000

That's more "load store architecture" than RISC. And by that measure, S/360 could be considered a RISC.

New comment by clausecker in "Addressing the adding situation"

clausecker — Wed, 03 Dec 2025 12:38:58 +0000

You may enjoy the RISC deprogrammer: https://blog.erratasec.com/2022/10/the-risc-deprogrammer.htm...

New comment by clausecker in "Poll HN: What operating system do you primarily develop on?"

clausecker — Fri, 28 Nov 2025 18:16:16 +0000

FreeBSD

New comment by clausecker in "FEX-emu – Run x86 applications on ARM64 Linux devices"

clausecker — Fri, 21 Nov 2025 19:35:29 +0000

ARM already has most stuff required for this on board. Two proprietary extensions are used by Rosetta: one emulates the parity (rarely used) and half-carry (obsolete) flags, which can also be emulated conventionally. The other implementa TSO memory ordering, which can either be ignored or implemented with explicit barriers; some other chips apparently have a similar setting.

The other stuff is all present in ARMv8.5 I think.

New comment by clausecker in "Fortran Outsmarted Our Billion-Dollar AI Chips"

clausecker — Mon, 10 Nov 2025 22:16:37 +0000

It's very likely that there is some serious autovectorisation going on behind the scenes.

New comment by clausecker in "End of Japanese community"

clausecker — Thu, 06 Nov 2025 11:46:54 +0000

Best one was when gedit had the option to syntax highlight for a language named “Los.”

New comment by clausecker in "Why every Rust crate feels like a research paper on abstraction"

clausecker — Sun, 19 Oct 2025 22:40:03 +0000

Had the same feeling browsing through the Haskell package collection. Felt like and almagamation of PhD theses, none of which were maintained after the author got his degree. Every single one a work of art, but most engeneered so badly that you would only use them begrudgingly.

New comment by clausecker in "Mysterious Intrigue Around an x86 "Corporate Entity Other Than Intel/AMD""

clausecker — Fri, 17 Oct 2025 00:26:39 +0000

Such as?

New comment by clausecker in "Comparing a RISC and a CISC with similar hardware organization (1991)"

clausecker — Thu, 09 Oct 2025 13:27:18 +0000

I'm talking about how they are able to integrate stuff that normally wouldn't fit into 32 bits (such as 3 operand simd with masking), not about getting the instruction set more compact. ARM knows how to do this (Thumb being the most compact mainstream ISA is evidence of that), they just have decided to waste a bit more space to make decoding simpler, while also adding more quality-of-life features.

New comment by clausecker in "Comparing a RISC and a CISC with similar hardware organization (1991)"

clausecker — Mon, 06 Oct 2025 11:20:43 +0000

Also, the VAX instruction encoding is a class of horror above that of x86.

New comment by clausecker in "Comparing a RISC and a CISC with similar hardware organization (1991)"

clausecker — Mon, 06 Oct 2025 11:17:16 +0000

ARM64 has a trick up its sleeve: many instructions that would be longer on other architecturea are instead split into easily recognisable pairs on ARM64. This allows for simple inplementations to pretend it's fixed length while more complex ones can pretend it's variable length. SVE takes this one step further with MOVPRFX, which can add be placed before almost all SVE instructions to supply masking and a third operand.

New comment by clausecker in "Comparing a RISC and a CISC with similar hardware organization (1991)"

clausecker — Mon, 06 Oct 2025 11:11:20 +0000

LL/SC is performant, it just doesn't scale to high core counts.

The VEX encoding is actually only rarely longer than the legacy one, and frequently it is shorter.

New comment by clausecker in "Processing Strings 109x Faster Than Nvidia on H100"

clausecker — Tue, 23 Sep 2025 13:51:40 +0000

When I implemented SIMD-accelerated string functions for FreeBSD's libc, I briefly looked at Stringzilla, but the code didn't look particularly interesting or fast. So no surprise here.