<rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Hacker News: davidlt</title><link>https://news.ycombinator.com/user?id=davidlt</link><description>Hacker News RSS</description><docs>https://hnrss.org/</docs><generator>hnrss v2.1.1</generator><lastBuildDate>Mon, 17 Aug 2026 07:49:07 +0000</lastBuildDate><atom:link href="https://hnrss.org/user?id=davidlt" rel="self" type="application/rss+xml"></atom:link><item><title><![CDATA[New comment by davidlt in "GLM-5.3: Frontier coding with emergent cyber capabilities"]]></title><description><![CDATA[
<p>It's the same pre-training, they are just adding more (+ better) SFT, RL, etc. (post-training). Model internal knowledge cut-off is still the same.<p>It seems we are doing pre-training every 6 months, and post-training every 4-8 weeks now.</p>
]]></description><pubDate>Fri, 14 Aug 2026 09:24:16 +0000</pubDate><link>https://news.ycombinator.com/item?id=49296405</link><dc:creator>davidlt</dc:creator><comments>https://news.ycombinator.com/item?id=49296405</comments><guid isPermaLink="false">https://news.ycombinator.com/item?id=49296405</guid></item><item><title><![CDATA[New comment by davidlt in "DeepSeek V4 Pro 0813"]]></title><description><![CDATA[
<p>I just wanted to emphasize this. Harness is a big part of how things perform thus usually it's harness + model co-design that's important.</p>
]]></description><pubDate>Wed, 12 Aug 2026 18:53:00 +0000</pubDate><link>https://news.ycombinator.com/item?id=49276953</link><dc:creator>davidlt</dc:creator><comments>https://news.ycombinator.com/item?id=49276953</comments><guid isPermaLink="false">https://news.ycombinator.com/item?id=49276953</guid></item><item><title><![CDATA[AMD Publishes Open-Source Driver for GPU Virtualization, Radeon "In the Roadmap"]]></title><description><![CDATA[
<p>Article URL: <a href="https://www.phoronix.com/news/AMD-GIM-Open-Source">https://www.phoronix.com/news/AMD-GIM-Open-Source</a></p>
<p>Comments URL: <a href="https://news.ycombinator.com/item?id=43779953">https://news.ycombinator.com/item?id=43779953</a></p>
<p>Points: 196</p>
<p># Comments: 61</p>
]]></description><pubDate>Thu, 24 Apr 2025 06:58:05 +0000</pubDate><link>https://www.phoronix.com/news/AMD-GIM-Open-Source</link><dc:creator>davidlt</dc:creator><comments>https://news.ycombinator.com/item?id=43779953</comments><guid isPermaLink="false">https://news.ycombinator.com/item?id=43779953</guid></item><item><title><![CDATA[New comment by davidlt in "Poland fumes over US block on AI chips"]]></title><description><![CDATA[
<p>This isn't a problem. See article [EN][0]. Simply put we are significantly below the cap. If somehow we would manage to hit the cap it definitely should be an alarm for investigation. I feel more folks are unhappy because EU was divided into two parts with this.<p>[0] <a href="https://www.lrt.lt/en/news-in-english/19/2461209/will-lithuania-be-affected-by-us-chip-export-controls" rel="nofollow">https://www.lrt.lt/en/news-in-english/19/2461209/will-lithua...</a></p>
]]></description><pubDate>Tue, 21 Jan 2025 12:48:37 +0000</pubDate><link>https://news.ycombinator.com/item?id=42779512</link><dc:creator>davidlt</dc:creator><comments>https://news.ycombinator.com/item?id=42779512</comments><guid isPermaLink="false">https://news.ycombinator.com/item?id=42779512</guid></item><item><title><![CDATA[New comment by davidlt in "Linux 6.11 Released"]]></title><description><![CDATA[
<p>I am really surprised with RNDA3 support. I have never seen so many issue with iGPU (APU). It started with VP9 decoder issue (e.g. just playing videos on YouTube was enough to trigger it), but that got fixed after a very long time (required a new firmware). Multiple constant [different] crashes, but you can workaround most of them by adding amdgpu.sg_display=0 to your bootargs. It's already listed in Arch Linux wiki, Gentoo wiki, etc.<p>Again, I was surprised by the number of firmware and driver issues since RNDA1/2/3 have been around for years now.</p>
]]></description><pubDate>Sun, 15 Sep 2024 19:11:46 +0000</pubDate><link>https://news.ycombinator.com/item?id=41549574</link><dc:creator>davidlt</dc:creator><comments>https://news.ycombinator.com/item?id=41549574</comments><guid isPermaLink="false">https://news.ycombinator.com/item?id=41549574</guid></item><item><title><![CDATA[New comment by davidlt in "Lichee Console 4A – RISC-V mini laptop: Review, benchmarks and early issues"]]></title><description><![CDATA[
<p>+1 on your initial comment. Exactly how I feel about the current situation.<p>MilkV Oasis with SG2380 would be the end-game for majority of developers, but they are definitely loosing money if they keep starting price at 120 USD. They don't have it frozen (they changed the SoC specification some weeks ago) thus I wouldn't be surprised to see this slip into 2025. I wouldn't be surprised if this outperforms MilkV Pioneer.</p>
]]></description><pubDate>Tue, 16 Jan 2024 11:10:59 +0000</pubDate><link>https://news.ycombinator.com/item?id=39011981</link><dc:creator>davidlt</dc:creator><comments>https://news.ycombinator.com/item?id=39011981</comments><guid isPermaLink="false">https://news.ycombinator.com/item?id=39011981</guid></item><item><title><![CDATA[New comment by davidlt in "Is RISC-V ready for HPC? Evaluating the 64-core Sophon SG2042 RISC-V CPU"]]></title><description><![CDATA[
<p>To my understanding SiFive continues to offer their selection of core IP. Anyways, I would assume any existing contract would have to be fulfilled for various legal reasons.<p>SG2042 itself is T-HEAD C920 design which is a mess, and might not be even called a RISC-V compliant design. We are kinda stuck it existing and being used in various chips. There are other design issues discovered IIRC (atomic might not work properly [at least on the kernel side workarounds required]; floating point failures in glibc testsuite because FP not being compliant). SG2044 is scheduled for the next year (2024). Not many details are known: 64 cores, 8 DDR controller, 3x memory bandwidth, vector v1.0 support, 2x PCIe (unknown what that means, Gen3 -> Gen4? More lanes?). The cores are unknown, but SG2038 is SiFive P670. T-HEAD has C908 that support vectors v1.0 (and solves some other issues), but that's a smaller core. Not a replacement for C910/C920.</p>
]]></description><pubDate>Sun, 10 Dec 2023 15:08:43 +0000</pubDate><link>https://news.ycombinator.com/item?id=38591977</link><dc:creator>davidlt</dc:creator><comments>https://news.ycombinator.com/item?id=38591977</comments><guid isPermaLink="false">https://news.ycombinator.com/item?id=38591977</guid></item><item><title><![CDATA[New comment by davidlt in "RISC-V SBC VisionFive 2 Officially Shipped"]]></title><description><![CDATA[
<p>Upstreasming status: <a href="https://rvspace.org/en/new-page/JH7110_Upstream_Plan" rel="nofollow">https://rvspace.org/en/new-page/JH7110_Upstream_Plan</a><p>StarFive Tech. have been upstreaming on kernel, OpenSBI and U-Boot from several weeks now. Of course this is still weeks/months away (if not more, for all the features) from landing in stable releases. Even more for distributions to pick those up.</p>
]]></description><pubDate>Wed, 11 Jan 2023 17:42:03 +0000</pubDate><link>https://news.ycombinator.com/item?id=34341518</link><dc:creator>davidlt</dc:creator><comments>https://news.ycombinator.com/item?id=34341518</comments><guid isPermaLink="false">https://news.ycombinator.com/item?id=34341518</guid></item><item><title><![CDATA[New comment by davidlt in "Intel completely disables AVX-512 on Alder Lake after all"]]></title><description><![CDATA[
<p>It could be that decision to not support AVX512 was made very late in product development and thus early batches didn't have chicken bit disabled or/and fused it off.<p>There might be gazillions of reason why this was done.</p>
]]></description><pubDate>Fri, 07 Jan 2022 13:55:00 +0000</pubDate><link>https://news.ycombinator.com/item?id=29839102</link><dc:creator>davidlt</dc:creator><comments>https://news.ycombinator.com/item?id=29839102</comments><guid isPermaLink="false">https://news.ycombinator.com/item?id=29839102</guid></item><item><title><![CDATA[New comment by davidlt in "HiFive Unmatched – A RISC-V Linux development platform"]]></title><description><![CDATA[
<p>Zba, Zbb, Zbc, Zbs  (BitManip) have been approved by "Architecture Review" thus I assume they close to being ratified. Probably one of the first new extensions to be available for RISC-V.<p>Because it's not ratified the BitManip extensions are not listed in any RISC-V Profiles as supported (or required). Platforms specification is also not requiring it.<p>Note that the next Profiles will be for 2022, thus any extension ratified before that most likely will appear in a new profile (i.e. as supported, non-conflicting extension) in some set.</p>
]]></description><pubDate>Fri, 10 Sep 2021 13:08:29 +0000</pubDate><link>https://news.ycombinator.com/item?id=28480983</link><dc:creator>davidlt</dc:creator><comments>https://news.ycombinator.com/item?id=28480983</comments><guid isPermaLink="false">https://news.ycombinator.com/item?id=28480983</guid></item><item><title><![CDATA[New comment by davidlt in "HiFive Unmatched – A RISC-V Linux development platform"]]></title><description><![CDATA[
<p>There are Profiles specs and Platforms specs, that will be regularly updated. This means software has a fixed target on which it can depend.</p>
]]></description><pubDate>Fri, 10 Sep 2021 12:55:53 +0000</pubDate><link>https://news.ycombinator.com/item?id=28480836</link><dc:creator>davidlt</dc:creator><comments>https://news.ycombinator.com/item?id=28480836</comments><guid isPermaLink="false">https://news.ycombinator.com/item?id=28480836</guid></item><item><title><![CDATA[New comment by davidlt in "HiFive Unmatched – A RISC-V Linux development platform"]]></title><description><![CDATA[
<p>I am running RX 570 with PCIe + 6-pin connector for the power. These works out-of-the-box due to open source drivers. Older Nvidia cards work too, but you would need to go with older cards as you need Nouveau driver. I believe someone recently used AMD RX 6700XT, which is a bit insane.<p>The bottleneck here is SoC, not the GPU. With HW decoding on the GPU I can play 4K 60fps trailers on Unmatched just fine.</p>
]]></description><pubDate>Fri, 10 Sep 2021 12:29:04 +0000</pubDate><link>https://news.ycombinator.com/item?id=28480563</link><dc:creator>davidlt</dc:creator><comments>https://news.ycombinator.com/item?id=28480563</comments><guid isPermaLink="false">https://news.ycombinator.com/item?id=28480563</guid></item><item><title><![CDATA[New comment by davidlt in "XuanTie C906 based Allwinner RISC-V processor to power $12 Linux SBC's"]]></title><description><![CDATA[
<p>For the price point they are going it's plenty enough. That's also enough to boot Linux distributions in headless mode.</p>
]]></description><pubDate>Mon, 09 Nov 2020 12:24:52 +0000</pubDate><link>https://news.ycombinator.com/item?id=25034006</link><dc:creator>davidlt</dc:creator><comments>https://news.ycombinator.com/item?id=25034006</comments><guid isPermaLink="false">https://news.ycombinator.com/item?id=25034006</guid></item><item><title><![CDATA[New comment by davidlt in "XuanTie C906 based Allwinner RISC-V processor to power $12 Linux SBC's"]]></title><description><![CDATA[
<p>IIRC Allwinner has already sent some patches related to RISC-V to kernel and also suggestions to SBI specification. So far the beginning is good. Remember that they are using IP from Alibaba. Alibaba might as well work on upstreaming, etc. efforts for this (speculation).</p>
]]></description><pubDate>Mon, 09 Nov 2020 12:22:24 +0000</pubDate><link>https://news.ycombinator.com/item?id=25033986</link><dc:creator>davidlt</dc:creator><comments>https://news.ycombinator.com/item?id=25033986</comments><guid isPermaLink="false">https://news.ycombinator.com/item?id=25033986</guid></item><item><title><![CDATA[New comment by davidlt in "XuanTie C906 based Allwinner RISC-V processor to power $12 Linux SBC's"]]></title><description><![CDATA[
<p>06:34PM EDT - Q: plans to support RVV 1.0? A: 0.7.1 for now - when we designed, it was still at that level. We are following and working on that yes.<p>From <a href="https://www.anandtech.com/show/15991/hot-chips-2020-live-blog-alibaba-xuantie910-riscv-cpu-300pm-pt" rel="nofollow">https://www.anandtech.com/show/15991/hot-chips-2020-live-blo...</a><p>0.7.1 and 1.0 will not be compatible IIRC thus Linux distribution most likely will not support RVV on this.</p>
]]></description><pubDate>Mon, 09 Nov 2020 12:20:24 +0000</pubDate><link>https://news.ycombinator.com/item?id=25033972</link><dc:creator>davidlt</dc:creator><comments>https://news.ycombinator.com/item?id=25033972</comments><guid isPermaLink="false">https://news.ycombinator.com/item?id=25033972</guid></item><item><title><![CDATA[Intel Releases Thunderbolt 3 Protocol (royalty-free) [base for USB 4]]]></title><description><![CDATA[
<p>Article URL: <a href="https://newsroom.intel.com/news/intel-takes-steps-enable-thunderbolt-3-everywhere-releases-protocol/">https://newsroom.intel.com/news/intel-takes-steps-enable-thunderbolt-3-everywhere-releases-protocol/</a></p>
<p>Comments URL: <a href="https://news.ycombinator.com/item?id=19301733">https://news.ycombinator.com/item?id=19301733</a></p>
<p>Points: 3</p>
<p># Comments: 0</p>
]]></description><pubDate>Mon, 04 Mar 2019 14:59:28 +0000</pubDate><link>https://newsroom.intel.com/news/intel-takes-steps-enable-thunderbolt-3-everywhere-releases-protocol/</link><dc:creator>davidlt</dc:creator><comments>https://news.ycombinator.com/item?id=19301733</comments><guid isPermaLink="false">https://news.ycombinator.com/item?id=19301733</guid></item><item><title><![CDATA[New comment by davidlt in "RFC 7858: DNS over TLS (2016)"]]></title><description><![CDATA[
<p>Yesterday I decided to configure unbound on fresh Fedora 28 Beta install and configure it to use DNS-over-TLS to Cloudflare and Quad9. unbound runs as local recursive resolver. Within a laptop it's decrypted, but all outside communications are over TLS (checked with wireshark). The 1st query for unknown domain is slow, ~300-1000 ms, but afterwards it always report 0ms. unbound in background should automatically update those record in the cache. So far works with no problems noticed.</p>
]]></description><pubDate>Tue, 10 Apr 2018 14:24:25 +0000</pubDate><link>https://news.ycombinator.com/item?id=16801583</link><dc:creator>davidlt</dc:creator><comments>https://news.ycombinator.com/item?id=16801583</comments><guid isPermaLink="false">https://news.ycombinator.com/item?id=16801583</guid></item><item><title><![CDATA[New comment by davidlt in "HiFive – RISC-V-based Linux development board"]]></title><description><![CDATA[
<p>We are working on Fedora RISC-V.</p>
]]></description><pubDate>Sun, 04 Feb 2018 09:34:10 +0000</pubDate><link>https://news.ycombinator.com/item?id=16302061</link><dc:creator>davidlt</dc:creator><comments>https://news.ycombinator.com/item?id=16302061</comments><guid isPermaLink="false">https://news.ycombinator.com/item?id=16302061</guid></item><item><title><![CDATA[FOSDEM 2018: Major SiFive Reveal in less than 12 hours (RISC-V)]]></title><description><![CDATA[
<p>You may have noticed a flurry of activity at SiFive over the past few days, or seen a tweet [0] or two [1] alluding to secretive and mysterious activity from Palmer and Yunsup! Here are the facts:<p>Palmer and Yunsup are, in fact, in Belgium at the moment
1. The FOSDEM Conference is also in Belgium (Coincidence?)
2. Both Palmer and Yunsup are enthusiastic Quake players 
3. RISC-V gossip circles are abuzz like never before
4. What does it all mean?<p>Tune in to the livestream of our upcoming presentation to find out! 
Saturday, 8am PST / 11am EST - Exactly 18 hours from now<p>Livestream: https://live.fosdem.org/watch/k1105<p>More:
- https://fosdem.org/2018/schedule/event/riscv/
- https://fosdem.org/2018/schedule/event/riscv_bof/<p>- - -<p>[0] https://twitter.com/SiFiveInc/status/959235164571389952
[1] https://twitter.com/SiFiveInc/status/959085220510171141</p>
<hr>
<p>Comments URL: <a href="https://news.ycombinator.com/item?id=16296381">https://news.ycombinator.com/item?id=16296381</a></p>
<p>Points: 1</p>
<p># Comments: 0</p>
]]></description><pubDate>Sat, 03 Feb 2018 05:46:38 +0000</pubDate><link>https://news.ycombinator.com/item?id=16296381</link><dc:creator>davidlt</dc:creator><comments>https://news.ycombinator.com/item?id=16296381</comments><guid isPermaLink="false">https://news.ycombinator.com/item?id=16296381</guid></item><item><title><![CDATA[New comment by davidlt in "The new microcode from Intel and AMD adds three new features"]]></title><description><![CDATA[
<p>IIUC, a limited number of people from kernel community knew about this and NDAs didn't exactly allow all the parties work together. The first solutions/mitigations exist (might not be nice), but now embargo is lifter and the communities (incl. companies) can work on better solutions together.</p>
]]></description><pubDate>Wed, 24 Jan 2018 08:13:20 +0000</pubDate><link>https://news.ycombinator.com/item?id=16221161</link><dc:creator>davidlt</dc:creator><comments>https://news.ycombinator.com/item?id=16221161</comments><guid isPermaLink="false">https://news.ycombinator.com/item?id=16221161</guid></item></channel></rss>