Hacker News: eigenform

New comment by eigenform in "SeL4 security proofs now complete on AArch64"

eigenform — Mon, 24 Aug 2026 22:12:19 +0000

What you want is a proof that microarchitectural timing differences (ie. the difference between a cache hit and cache miss) cannot possibly turn into architecturally-visible timing differences. If a program cannot reliably distinguish between two points in time, time is not a suitable channel for programs.

You could have an ISA where timing information is simply not presented to the programmer, but programmers like being able to profile their programs.

New comment by eigenform in "Xiaomi: New CPU matches Apple cores single threaded, much faster multithreaded"

eigenform — Mon, 24 Aug 2026 21:25:43 +0000

It's good to be skeptical about how we implement the idea of a "root of trust" in these machines, but matter-of-factly characterizing ME and PSP as "backdoor" is misleading and not useful.

New comment by eigenform in "Fixing a bricked Framework laptop"

eigenform — Tue, 18 Aug 2026 22:34:58 +0000

So did anyone actually figure out what the issue was?

New comment by eigenform in "A new Intel Itanium (IA-64) emulator that boots Windows"

eigenform — Thu, 23 Jul 2026 03:53:09 +0000

Sorry, when talking about things from the hardware's point of view, I'm in the habit of using the word "programmer" to also mean "the compiler"!

New comment by eigenform in "A new Intel Itanium (IA-64) emulator that boots Windows"

eigenform — Mon, 20 Jul 2026 18:20:18 +0000

Yes, I'm pointing out the fact that the programmer is expected to manage the ALAT, and that these machines do not automatically recover from cases where your advanced loads are incorrect. That process is expected to be part of the instruction stream, and [we have collectively learned that] that's an expensive feedback loop.

Yes, it doesn't require determinism to work, but it means that your performance is especially sensitive to nondeterminism because the compiler cannot account for loads and stores that occur online. The SDM (see vol 1, section 9.5.1) describes this idea pretty well.

New comment by eigenform in "A new Intel Itanium (IA-64) emulator that boots Windows"

eigenform — Mon, 20 Jul 2026 08:23:04 +0000

The difference is that this is not the programmer's responsibility in modern machines: instead we bake-in some hardware that watches the online state of the machine and then actively decides on what to do.

If you're trying to create a compiler that approaches the effectiveness of this statically, you're condemned to do a ton of extra work (you're essentially writing an emulator for your CPU core, and then a compiler that uses that model to produce optimal code - even then, you might not be accounting for nondeterminism on the actual target machine, and some information is simply not accessible to you when you are not on the target machine)

New comment by eigenform in "AMD silently removes memory encryption from consumer Ryzen CPUs"

eigenform — Thu, 18 Jun 2026 22:49:32 +0000

Additionally, if you look at the changelogs for old ABL, it seems like this policy decision (only supporting for PRO SKUs) has always been implemented in firmware:

https://github.com/amd/firmware_binaries/blob/main/cezanne/P...

AFAICT the situation here is, it should have never been enabled for these consumer parts in the first place.

New comment by eigenform in "Bug 1950764: Work Around Crash on Intel Raptor Lake CPU"

eigenform — Mon, 25 May 2026 18:30:59 +0000

Well, the FDIV bug is simpler. AFAICT this whole thing is tied up in the relationship between DVFS, silicon aging, and being able to have guarantees about clock reliability. That seems hard to reason about when you give BIOS vendors and users the ability to do over-volting/over-clocking (and of course, it's worse when you are maybe relying on all this in certain situations to try and approach parity with other hardware vendors who are taping out machines on CMOS processes that are more mature than yours).

New comment by eigenform in "M 7.4 earthquake – 100 km ENE of Miyako, Japan"

eigenform — Tue, 21 Apr 2026 05:26:35 +0000

afaict part of the messaging behind this quake is about the worry that big Sanriku earthquakes like this might make it easier for the northeast part of the trench to unlock (closer to Aomori and Hokkaido, where the Japan Trench starts turning into the Kuril Trench).

New comment by eigenform in "M 7.4 earthquake – 100 km ENE of Miyako, Japan"

eigenform — Tue, 21 Apr 2026 04:57:39 +0000

No reason that the rate of subduction has to be the same everywhere. Some of the plate boundaries might be moving into each other in different directions too, the coupling between plates is not necessarily the same everywhere.

Anyway, in the case of Cascadia, remember that the lack of big earthquakes over the past 100 years is probably telling you that we just happen to live in a time where strain is accumulating (D:)

New comment by eigenform in "How many branches can your CPU predict?"

eigenform — Fri, 20 Mar 2026 08:43:52 +0000

The idea here is about maintaining a "path history"!

When looking up a register that tracks the "local" history of outcomes for a particular branch, you want to have a hash function that captures enough context to distinguish the different situations where that branch might be encountered.

Apart from folding a long "global history" of recent outcomes and mixing in the current program counter, I think many modern machines also mix in the target addresses of recently-taken branches.

The most precise mechanical indicators ever made – The Mikrokator [video]

eigenform — Wed, 07 Jan 2026 01:39:13 +0000

Article URL: https://www.youtube.com/watch?v=_HIKmxHcxkg

Comments URL: https://news.ycombinator.com/item?id=46521438

Points: 3

# Comments: 0

New comment by eigenform in "An abstract knot finite state machine"

eigenform — Tue, 06 Jan 2026 23:21:13 +0000

please stop posting worthless drivel from your language model, thank you. it really cheapens the meaning of all these fancy words.

New comment by eigenform in "CES 2026: Taking the Lids Off AMD's Venice and MI400 SoCs"

eigenform — Tue, 06 Jan 2026 23:12:20 +0000

ie. marketed as "dense" instead of "efficient"

New comment by eigenform in "ChkTag: x86 Memory Safety"

eigenform — Tue, 21 Oct 2025 01:05:40 +0000

Probably because it's very likely that both AMD and Intel have had engineers working on this sort of thing for a long time, and they're now deciding to collectively hash out whatever the solution is going to be for both of them.

New comment by eigenform in "ChkTag: x86 Memory Safety"

eigenform — Tue, 21 Oct 2025 01:02:34 +0000

I'm not arguing MPX was a good solution, just that it's silly to assume folks designing x86 machines have been totally ignoring developments in that space for the past ten years.

New comment by eigenform in "ChkTag: x86 Memory Safety"

eigenform — Mon, 20 Oct 2025 23:05:09 +0000

fwiw "knee-jerk reaction to Apple MIE" is not exactly the right characterization of this. MPX existed and faded away, and it's not very surprising that x86-world would wait for someone else to try shipping hardware support for memory safety features before trying again.

New comment by eigenform in "Mysterious Intrigue Around an x86 "Corporate Entity Other Than Intel/AMD""

eigenform — Thu, 16 Oct 2025 18:07:39 +0000

I wonder if this is in response to FineIBT trying to figure out what to use as an undefined opcode? Apparently 0xd6 is being reserved as undefined going forward:

https://lore.kernel.org/lkml/20250814111732.GW4067720@noisy....

New comment by eigenform in "Comparing a RISC and a CISC with similar hardware organization (1991)"

eigenform — Sun, 05 Oct 2025 21:34:14 +0000

Yeah totally. It's really easy to forget about the fact that x86 is abstracting a lot of stack operations away from you (and obviously that's part of why it's a useful abstraction!).

New comment by eigenform in "Comparing a RISC and a CISC with similar hardware organization (1991)"

eigenform — Sun, 05 Oct 2025 21:12:04 +0000

> x86 CALL/RET

I wonder if anyone has actually measured what the code size savings from this look like for typical programs, that would be an interesting read. RISC trope is to expose a "link register" and expect the programmer to manage storage for a return address, but if call/ret manage this for you auto-magically you're at least saving some space whenever dealing with non-leaf functions.