Live migration support may be the reason why they stick to the baseline. That's most likely to be migratable across different CPU types. Although with a bit of effort, you can figure out what is support by your fleet and configure that into the hypervisors.

I'm skeptical that pre-SSE-4.2 etc. CPUs are economically viable for running customer workloads due to electricity costs.

For many other things, like using a YMM register to copy a 32-byte struct or a variable shift, run-time dispatch just not make sense. You will only see a benefit if you generate this code unconditionally. For FMA, you wouldn't even get bit-identical output, leading to testing concerns.

For teachers, other things matter more than reasoning skills or subject matter knowledge, especially in rural or otherwise challenging communities.

There are similar offerings from other companies. I don't know if bundling this with payment processing is common.

> Only an extremely purposeful crew with a good comprehension of the situation could have carried out a manoeuvre that would have made it possible to perhaps recover control of the aeroplane. In fact, the crew had almost completely lost control of the situation.

I had no idea that things could go wrong so quickly, even at that altitude.

I'm excited about Nova Lake as well. Maybe not so much for the EGPRs (maybe we should have made 4 of the new registers callee-saved?), but there are other goodies as well.

For example, Intel stated this:

> Intel® Advanced Vector Extensions 10 (Intel® AVX10) introduces a modern vector Instruction Set Architecture (ISA) that will be supported across future Intel® processors.

They don't actually say “all”, and it is probably meant to apply to future microarchitectures anyway. Depending on various factors, Intel may end up designing new CPUs based on existing microarchitectures well into the 2030s.

The latter could at least be solved with some community effort, although the relevant set of instructions is quite large. It's also not specific to AVX-512. Any comparable vector ISA faces the same challenge.

Hopefully, one of these systems gets produced in such large quantities that there's some pressure to add mainline Linux support.

I still don't have an explanation why people are doing this. Is it part of leadership training? Or do presenters have their own theory that including this stuff makes the presentation more memorable and enjoyable?

> By now the airspeed indications had returned to normal, but the pilots had already set in motion a sequence of events which could not be undone.

That was before the prolonged stall warnings. But maybe this phrasing is just an embellishment?

But further down, the article is pretty clear that the training was inadequate for this type of unreliable airspeed indication:

> Although procedures for other phases of flight could be found in the manual, the training conditioned pilots to expect unreliable airspeed events during climb, to which they would respond with a steady nose-up pitch and high power setting that would ensure a shallow ascent. Such a response would be completely inappropriate in cruise.