Hacker News: icelusxl

New comment by icelusxl in "Win16 Memory Management"

icelusxl — Sun, 07 Jun 2026 13:37:52 +0000

Memory mapping/bank switching was fairly common on 8-bit and 16-bit systems, where a small memory window was used to select different memory banks, allowing a program to access more memory in chunks.

Game consoles like NES, SNES and Game Boy had additional hardware built in the cartridge to support memory mapping/bank switching.

For PCs, EMS (memory) provided a similar concept. It reserved a 64 kB window divided in 16 kB pages in the first 1 MB and allowed to map up to 32 MB.

New comment by icelusxl in "Windows GOG DOS Games on M-Series Macs"

icelusxl — Mon, 01 Jun 2026 19:03:20 +0000

> There are only a handful of different instructions that account for 90% of all operations executed, and, near the top of that list are addition and subtraction. On ARM these can optionally set the four-bit NZCV register, whereas on x86 these always set six flag bits: CF, ZF, SF and OF (which correspond well-enough to NZCV), as well as PF (the parity flag) and AF (the adjust flag).

> Emulating the last two in software is possible (and seems to be supported by Rosetta 2 for Linux), but can be rather expensive. Most software won’t notice if you get these wrong, but some software will. The Apple M1 has an undocumented extension that, when enabled, ensures instructions like ADDS, SUBS and CMP compute PF and AF and store them as bits 26 and 27 of NZCV respectively, providing accurate emulation with no performance penalty.

https://dougallj.wordpress.com/2022/11/09/why-is-rosetta-2-f...

New comment by icelusxl in "Let's compile Quake like it's 1997"

icelusxl — Fri, 29 May 2026 09:38:24 +0000

Yes, Turbo Pascal 5.0 introduced those features in 1988.

https://www.youtube.com/watch?v=UNx4dxXptUg

New comment by icelusxl in "macOS 27 won’t be supporting Intel anymore"

icelusxl — Mon, 20 Apr 2026 13:11:50 +0000

Virtualize macOS 26 for testing purposes: https://eclecticlight.co/2025/01/21/what-can-you-do-with-vir...

New comment by icelusxl in "Too much discussion of the XOR swap trick"

icelusxl — Thu, 16 Apr 2026 08:19:42 +0000

It still is. The CPU's register renamer can detect these instructions to not have data dependencies and can zero the register itself. It doesn't send the instruction to the execution engine meaning they use no execution resources and have zero latency.

New comment by icelusxl in "Microsoft hasn't had a coherent GUI strategy since Petzold"

icelusxl — Mon, 06 Apr 2026 18:02:17 +0000

The "Performance Improvements in .NET" blog lists the new JIT support for instruction sets each year.

https://devblogs.microsoft.com/dotnet/performance-improvemen...

New comment by icelusxl in "AVX Bitwise ternary logic instruction busted"

icelusxl — Mon, 07 Oct 2024 06:07:14 +0000

Also supported in .NET 9

* https://devblogs.microsoft.com/dotnet/performance-improvemen...

* https://github.com/dotnet/runtime/pull/91227

New comment by icelusxl in "Bit Twiddling Hacks (2009)"

icelusxl — Fri, 23 Aug 2024 09:19:39 +0000

Maybe http://0x80.pl -- this site features mainly SIMD/SWAR code.

New comment by icelusxl in "Chrome: Heap buffer overflow in WebP"

icelusxl — Tue, 12 Sep 2023 09:46:47 +0000

Seems to be reported by Apple and looks a lot like this security update: https://support.apple.com/en-us/HT213906

New comment by icelusxl in "Popcount CPU instruction (2019)"

icelusxl — Sun, 13 Aug 2023 18:27:55 +0000

> "rotate and mask" series of instructions

Sounds a lot like the PowerPC's rlwinm instruction.

The PowerPC 600 series, part 5: Rotates and shifts

https://devblogs.microsoft.com/oldnewthing/20180810-00/?p=99...

New comment by icelusxl in "RISC-V Instructions"

icelusxl — Mon, 10 Jul 2023 08:50:33 +0000

"rep stosb" has been optimized since Ivy Bridge CPUs.

> Beginning with processors based on Ivy Bridge microarchitecture, REP string operation using MOVSB and STOSB can provide both flexible and high-performance REP string operations for software in common situations like memory copy and set operations.

> Beginning with processors based on Ice Lake Client microarchitecture, REP MOVSB performance of short operations is enhanced. The enhancement applies to string lengths between 1 and 128 bytes long.

* https://www-ssl.intel.com/content/www/us/en/architecture-and...

* https://stackoverflow.com/a/33485055

New comment by icelusxl in "Dynamic bit shuffle using AVX-512"

icelusxl — Fri, 30 Jun 2023 13:47:21 +0000

* Visualization: https://www.officedaytime.com/simd512e/

* Book: https://link.springer.com/book/10.1007/978-1-4842-4063-2

New comment by icelusxl in "Amazon EC2 M1 Mac Instances"

icelusxl — Thu, 02 Dec 2021 17:57:56 +0000

€49/month at Hetzner.

https://www.hetzner.com/dedicated-rootserver/matrix-apple