<rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Hacker News: jeff_ciesielski</title><link>https://news.ycombinator.com/user?id=jeff_ciesielski</link><description>Hacker News RSS</description><docs>https://hnrss.org/</docs><generator>hnrss v2.1.1</generator><lastBuildDate>Mon, 28 Sep 2026 12:14:22 +0000</lastBuildDate><atom:link href="https://hnrss.org/user?id=jeff_ciesielski" rel="self" type="application/rss+xml"></atom:link><item><title><![CDATA[New comment by jeff_ciesielski in "Jev in 25 Lines of Python"]]></title><description><![CDATA[
<p>This works very very well :).<p><a href="https://github.com/Mushroom-Systems/lichen" rel="nofollow">https://github.com/Mushroom-Systems/lichen</a></p>
]]></description><pubDate>Wed, 23 Sep 2026 21:24:27 +0000</pubDate><link>https://news.ycombinator.com/item?id=49822809</link><dc:creator>jeff_ciesielski</dc:creator><comments>https://news.ycombinator.com/item?id=49822809</comments><guid isPermaLink="false">https://news.ycombinator.com/item?id=49822809</guid></item><item><title><![CDATA[New comment by jeff_ciesielski in "A FPGA friendly 32 bit RISC-V CPU implementation"]]></title><description><![CDATA[
<p>We do a fair bit of FPGA design in SpinalHDL, and have taped out several ASICs with parts of the design done in SpinalHDL at my dayjob.<p>In general: No, alternative HDLs don't see a lot of use, and I'd argue that we qualify as 'academia' since the ASICs are NIH funded and we tend to work with a lot of academic partners and on low-quantity R&D projects.<p>Having said that, every time we've deployed SpinalHDL for a commercial client they've been blown away by the results.  The standard library, developer ergonomics, test capabilities, and little things like having clock domains as a part of the type system make development so much faster and less error prone that the NRE for doing it in verilog just doesn't make sense.<p>You get access to the entire Java and Scala ecosystem at elaboration and test time.  We deploy ScalaCheck in our test harnesses to automatically generate test cases that can reduce inputs to identify edge cases.  It's incredibly powerful.</p>
]]></description><pubDate>Sat, 25 Jan 2025 20:34:55 +0000</pubDate><link>https://news.ycombinator.com/item?id=42824613</link><dc:creator>jeff_ciesielski</dc:creator><comments>https://news.ycombinator.com/item?id=42824613</comments><guid isPermaLink="false">https://news.ycombinator.com/item?id=42824613</guid></item><item><title><![CDATA[New comment by jeff_ciesielski in "MicroZig: Unified abstraction layer and HAL for Zig on several microcontrollers"]]></title><description><![CDATA[
<p>Like any time you get off the beaten path, there are rough patches, but to paraphrase another comment in this thread "Nim is just C", so anything that felt a little awkward just meant using an `importc` pragma and doing whatever I needed to do in an environment I felt more comfortable (you can also have C code compiled with a {.compile: "foo.c"} pragma, so if a module required something be done in C, you didn't have to monkey about with the build system to include it, it 'just worked')<p>The biggest negative I ever hit was that early on, Nim didn't have support for `volatile`, which meant it was a non-starter for doing anything with MMIO (I ended up being the one who added volatileLoad/volatileStore to Nim's stdlib so I could use it on a Cortex-M without having to drop into C so much).<p>For the most part though, if you're reasonably comfortable with embedded toolchains (i.e. you understand how to write linker scripts, understand what happens between a reset and actually getting into `main()`, etc), it's not much of a hurdle to set up a simple build system to compile your Nim code to C, link appropriately, and then sort of forget about it.<p>It's been a while, but IIRC I also got step-through debugging working with OpenOCD by having the nim compiler generate `#line` pragmas and including debug symbols, which was pretty neat.<p>This was all pre ARC/ORC, so I did have to make sure to be careful not to use ref objects, but  ultimately it felt pretty seamless. I still tend towards fully manually managed memory on embedded projects, but I'd be curious to give it a go.</p>
]]></description><pubDate>Thu, 29 Feb 2024 17:23:32 +0000</pubDate><link>https://news.ycombinator.com/item?id=39552286</link><dc:creator>jeff_ciesielski</dc:creator><comments>https://news.ycombinator.com/item?id=39552286</comments><guid isPermaLink="false">https://news.ycombinator.com/item?id=39552286</guid></item><item><title><![CDATA[New comment by jeff_ciesielski in "MicroZig: Unified abstraction layer and HAL for Zig on several microcontrollers"]]></title><description><![CDATA[
<p>> In what way? Comptime should be generally capable of anything macros are.<p>I started to reply to this with 'Comptime is generally capable of doing anything that Nim's templates can accomplish (but not it's macros)', but I stopped myself because even though Zig's comptime is more akin to Nim's templates than its macros (in my opinion), Nim templates are more powerful as they allow you to embed arbitrary blocks of code to implement constructs similar to python's context managers (which I'm fairly certain you can't do with comptime).<p>W/R/T Macros vs Comptime, you can't create arbitrarily complex DSLs with comptime the way you can with a Nim's macros as you don't have full control over AST generation.<p>All that said, the power you'd get from a Macro or Template system like Nim's don't really jive with Zig's whole "no hidden control flow" thing.<p>>Terribly difficult to implement without breaking a major language tenant of “no hidden control flow”.<p>I dunno if I agree with that, even very simple rust-like traits that simply enforce that a struct implemented a given interface at compile time (static dispatch only) would go a long way without compromising obvious control flow IMO.<p>>But I found that once I left behind OO style of thinking, I haven’t missed this all that much. For the rare time I do generalize like this, you can literally just check at comptime that the passed in type provides the necessary decls. It’s not terribly complex or hostile (although tooling could use some work around it)<p>Respectfully, I don't view it as OO thinking (I think typeclasses come from SML...). Making polymorphism reasonably ergonomic goes a long way towards code reuse and (again, only my humble opinion here) would help with what some of the folks in this comment section are talking about w/r/t code re-use and generalizing a HAL layer in a consistent way without forcing users (or library authors) to write a bunch of ad-hoc code to check that functions exist on a given struct, or manually implementing dispatch tables.</p>
]]></description><pubDate>Wed, 28 Feb 2024 23:40:54 +0000</pubDate><link>https://news.ycombinator.com/item?id=39544946</link><dc:creator>jeff_ciesielski</dc:creator><comments>https://news.ycombinator.com/item?id=39544946</comments><guid isPermaLink="false">https://news.ycombinator.com/item?id=39544946</guid></item><item><title><![CDATA[New comment by jeff_ciesielski in "MicroZig: Unified abstraction layer and HAL for Zig on several microcontrollers"]]></title><description><![CDATA[
<p>I used Zig (not MicroZig, just rolled my own HAL) for the bootloader and firmware on a soft RISC-V SOC + custom peripherals recently and had somewhat mixed, though positive feelings about it.<p>On the positive side:<p>- As a 'safer c', getting things up and running was a breeze, writing code largely felt intuitive.<p>- The additions to C (slices/iterators, enhanced structs, arbitrarily sized integers) are excellent<p>- It produces fairly small firmware images (useful when stuffing a boot rom in logic/EBRAM)<p>- Easier (than C IMO) to get up and running with formatted IO vs retargeting libc<p>- Comptime is neat, and you can build some decent low-cost abstractions with it (ex: I built a comptime heavy write-through cache for key-value  storage that required very little overhead and largely self-generated based on a simple struct)<p>- I really enjoy the use of structs for function+data organization. It maps well to hardware instances, giving you an 'object' like feeling without OOP ick.<p>On the negative side:<p>- The compiler is still a seriously moving target. Upgrading sometimes meant rather large refactors.<p>- Documentation is somewhat poor IMO.<p>- As a long time user of Nim (including on really lean embedded targets), compared to hygienic macros, comptime falls way short.<p>- The lack of first class interfaces/traits/typeclasses is not my favorite.  The currently suggested alternatives are so un-ergonomic I'd almost call them hostile.<p>All-in-all, I'm excited to see where Zig ends up. After nearly 20 years writing embedded code I'm really (really really really) tired of C. The embedded systems community really needs to embrace better tools.</p>
]]></description><pubDate>Wed, 28 Feb 2024 21:45:41 +0000</pubDate><link>https://news.ycombinator.com/item?id=39543854</link><dc:creator>jeff_ciesielski</dc:creator><comments>https://news.ycombinator.com/item?id=39543854</comments><guid isPermaLink="false">https://news.ycombinator.com/item?id=39543854</guid></item><item><title><![CDATA[New comment by jeff_ciesielski in "How many Devices can you Connect to the I2C Bus?"]]></title><description><![CDATA[
<p>This is a nice breakdown, however it is leaving out one interesting piece: Active slew rate controllers.<p>In some cases where you need to exceed the typically allowed bus capacitance either due to a high number of attached devices, or over a long cable run (it happens...it sucks, but it happens), you can use a part like the LTC4311 which, rather than using resistors to passively pull the bus lines to a resting high state, detects the direction changes and actively assists in pulling the lines to their intended states.<p><a href="https://www.analog.com/media/en/technical-documentation/data-sheets/4311fa.pdf" rel="nofollow">https://www.analog.com/media/en/technical-documentation/data...</a></p>
]]></description><pubDate>Tue, 13 Apr 2021 13:48:38 +0000</pubDate><link>https://news.ycombinator.com/item?id=26792073</link><dc:creator>jeff_ciesielski</dc:creator><comments>https://news.ycombinator.com/item?id=26792073</comments><guid isPermaLink="false">https://news.ycombinator.com/item?id=26792073</guid></item><item><title><![CDATA[New comment by jeff_ciesielski in "How many Devices can you Connect to the I2C Bus?"]]></title><description><![CDATA[
<p>I hate to give an 'it depends', but it depends.<p>Typically, no. In SPI all lines are actively driven high or low rather than an open drain configuration.  The bus master drives SCK (SPI clock), MOSI (master out, slave in) and CS (chip select), and the slave device(s) drive the MISO (master in, slave out) line(s). From an operating perspective, pullup/pulldown resistors are not required.<p>Now having said that, in some cases it's considered appropriate to add weak pullup/pulldown resistors to the data lines to ensure that they're in the expected state on power up and to prevent glitches from putting slave devices into weird states.</p>
]]></description><pubDate>Tue, 13 Apr 2021 13:44:41 +0000</pubDate><link>https://news.ycombinator.com/item?id=26792029</link><dc:creator>jeff_ciesielski</dc:creator><comments>https://news.ycombinator.com/item?id=26792029</comments><guid isPermaLink="false">https://news.ycombinator.com/item?id=26792029</guid></item><item><title><![CDATA[New comment by jeff_ciesielski in "Lion: A formally verified, 5-stage pipeline RISC-V core"]]></title><description><![CDATA[
<p>(From someone who is working on a rv32im implementation in Clash)<p>I really love writing RTL in haskell when compared to verilog/vhdl, but as a language I think it suffers from the same thing a lot of other languages do: too many ways to do the same thing. Mix that with a language that encourages meta-programming and you've got yourself a recipe for every complex haskell project basically becoming it's own little DSL. It's also often made worse because so much haskell is written by type-theorists and mathematicians churning out symbol-soup without a thought for the rest of us plebs.<p>IMO this is actually pretty readable and the implementation is stitched together nicely. There are some haskell/ml-isms like lenses/monad transformers/partial functions sprinkled in there that complicate a casual read-through, but if you've got a grasp on those most of this is reasonably clear.<p>It isn't the most complex beast (as others have pointed out, it skips things like the Zicsr and M extensions which add significant complexity) but it could serve very well as say, a companion core to some more complex piece of hardware. Perhaps one that requires reconfigurable logic that would be impractical in silicon but doesn't require realtime interrupts or fast math?</p>
]]></description><pubDate>Thu, 04 Mar 2021 15:23:24 +0000</pubDate><link>https://news.ycombinator.com/item?id=26343522</link><dc:creator>jeff_ciesielski</dc:creator><comments>https://news.ycombinator.com/item?id=26343522</comments><guid isPermaLink="false">https://news.ycombinator.com/item?id=26343522</guid></item><item><title><![CDATA[New comment by jeff_ciesielski in "Compiling at Compile Time"]]></title><description><![CDATA[
<p>I wrote something similar a while back (also in nim):
<a href="https://github.com/Jeff-Ciesielski/synesthesia" rel="nofollow">https://github.com/Jeff-Ciesielski/synesthesia</a><p>When I stop being so darn busy, I do want to revisit my original project of doing the same thing for a FORTH derivative.</p>
]]></description><pubDate>Thu, 07 Nov 2019 23:05:34 +0000</pubDate><link>https://news.ycombinator.com/item?id=21478248</link><dc:creator>jeff_ciesielski</dc:creator><comments>https://news.ycombinator.com/item?id=21478248</comments><guid isPermaLink="false">https://news.ycombinator.com/item?id=21478248</guid></item><item><title><![CDATA[New comment by jeff_ciesielski in "Ask HN: Who is hiring? (November 2019)"]]></title><description><![CDATA[
<p>KeyMe | (Sr) Software Engineer(s) | New York, New York | Full-Time | ONSITE | key.me<p>KeyMe manufactures and operates a nation-wide fleet of robotic key cutting kiosks and seeks to provide fast accurate key duplication, digital key storage to prevent lockouts, and full-service locksmith services for non-key related needs.<p>We're looking to grow our control systems team to continue to scale out our fleet of kiosks.  In the last 3 years we've grown 10x, and are on track to double our install base again next year.  We offer a wide variety of engineering activities and have a great team working on some extremely challenging problems (remotely administering 5k robots on cell modems? Live configuration sync between 5k nodes and a central server with varying latency?).  Our tech stack is primarily Python3|Haskell|Linux and we're looking to add some folks with Docker | RabbitMQ | FP experience (any FP language is fine).<p>If you're interested in working with robotics and hardware AND have an interest in functional programming, I'd love to hear from you.
Feel free to check out our job posting: <a href="https://boards.greenhouse.io/keyme/jobs/4266786002" rel="nofollow">https://boards.greenhouse.io/keyme/jobs/4266786002</a>
Or contact me directly: jeff.ciesielski[at]key.me<p>(We will also have some additional roles opening up in the very neat future, so if you're a CV / ML / Data engineer, I'd love to hear from you too!)</p>
]]></description><pubDate>Sat, 02 Nov 2019 12:42:10 +0000</pubDate><link>https://news.ycombinator.com/item?id=21427334</link><dc:creator>jeff_ciesielski</dc:creator><comments>https://news.ycombinator.com/item?id=21427334</comments><guid isPermaLink="false">https://news.ycombinator.com/item?id=21427334</guid></item><item><title><![CDATA[Show HN: Synesthesia – Optimizing brainfuck compiler implemented as Nim macros]]></title><description><![CDATA[
<p>Article URL: <a href="https://github.com/Jeff-Ciesielski/synesthesia">https://github.com/Jeff-Ciesielski/synesthesia</a></p>
<p>Comments URL: <a href="https://news.ycombinator.com/item?id=19133796">https://news.ycombinator.com/item?id=19133796</a></p>
<p>Points: 33</p>
<p># Comments: 3</p>
]]></description><pubDate>Mon, 11 Feb 2019 12:03:06 +0000</pubDate><link>https://github.com/Jeff-Ciesielski/synesthesia</link><dc:creator>jeff_ciesielski</dc:creator><comments>https://news.ycombinator.com/item?id=19133796</comments><guid isPermaLink="false">https://news.ycombinator.com/item?id=19133796</guid></item></channel></rss>