Hacker News: mshockwave

New comment by mshockwave in "Valen's Memory Safety: A New Kind of Borrow Checking"

mshockwave — Sun, 11 Oct 2026 21:31:49 +0000

is it the mech-lang?

New comment by mshockwave in "MongoDB CEO resigns to join Meta"

mshockwave — Mon, 28 Sep 2026 15:43:41 +0000

in case anyone who doesn't get the reference: https://youtu.be/b2F-DItXtZs?si=gxrqufTAy-YQ88wW

New comment by mshockwave in "Platform-independent SIMD in Go"

mshockwave — Fri, 25 Sep 2026 20:54:42 +0000

> constrain the length to the maximum vector size supported by the lowest platform you want to support or you lose the portability and actually end up with code that performs much worse than the scalar alternative on some platforms.

Or, put a dynamic factor into your vector size and design everything around it. Such that every platforms can plug in their own factor and _scale_ the size of vectors. This is basically what LLVM IR does for SVE and RVV: `` where vscale is the said dynamic factor. Though the exact value of vscale is only known during runtime, it doesn't matter -- we still can design compiler optimizations and lowering around it. The generated binaries can then be portable across platforms with different vscale values.

New comment by mshockwave in "Platform-independent SIMD in Go"

mshockwave — Fri, 25 Sep 2026 16:59:05 +0000

Just want to say among many portable SIMD solutions I’ve seen recently (e.g. Fearless SIMD), this is the first that makes non-fixed vectors like SVE and RISC-V vector (RVV) easier to support. Glad to see they made this decision

RISC-V Extension Landscape

mshockwave — Tue, 18 Aug 2026 01:11:14 +0000

Article URL: https://rpsene.github.io/riscv-extensions-landscape/

Comments URL: https://news.ycombinator.com/item?id=49339890

Points: 4

# Comments: 0

New comment by mshockwave in "A third world engineer responds to “RISC-V: They should have known better”"

mshockwave — Sun, 16 Aug 2026 20:27:58 +0000

I disagree, compiler optimization and software ecosystem in general already take a really really really long time to build, and I think it'll take longer without a standardized low-level binary interface i.e. ISA to enable rapid distribution.

And the approach you mentioned here:

> a family of ISAs that are ABI compatible such that one can compile down to a semi-pre-optimized portable IR, and just do the last bit per ISA

I think this is basically WebAssembly and PTX, and one may argue, Java bytecode. Yet look at how much efforts and time it took for WASM runtimes and JVMs to actually produce performant machine code (the "last bit per ISA" you mentioned) for just a couple of architectures! (e.g. X86 and ARM). And I wouldn't surprised if NVIDIA pour even more money on building optimization pipeline from PTX to each of their different uArchs.

RVV Benchmark SiFive P870 (Lanxin LX500, Epic Semi Contrail AIx)

mshockwave — Thu, 06 Aug 2026 14:23:25 +0000

Article URL: https://camel-cdr.github.io/rvv-bench-results/sifive_p870/index.html

Comments URL: https://news.ycombinator.com/item?id=49197103

Points: 1

# Comments: 0

New comment by mshockwave in "Deep-sea vehicles spot 'alien' sharks deep beneath the waves in the Pacific"

mshockwave — Sun, 02 Aug 2026 05:49:22 +0000

or have little vision to begin with

New comment by mshockwave in "Qualcomm to Acquire Modular"

mshockwave — Thu, 25 Jun 2026 14:33:17 +0000

one of the reasons I rarely read press releases is that I don't believe in promises -- I believe in _incentives_. In this case, what will Qualcomm be incentivized to do? What are in their interests?

New comment by mshockwave in "Qualcomm to Acquire Modular"

mshockwave — Thu, 25 Jun 2026 14:23:53 +0000

indeed, open sourcing is only half (or even less) of the picture: who is driving the open source community and how it is driven (i.e. governing structure) are probably more important IMHO. There are countless of cases where an open source project is either killed by slow death, or dictated by a single entity. Chris's previous projects like LLVM and MLIR are fortunate enough to grow and thrive organically, and that takes years if not decades to cultivate

New comment by mshockwave in "How Mark Klein told the EFF about Room 641A [book excerpt]"

mshockwave — Fri, 01 May 2026 02:56:11 +0000

it's a book excerpt

New comment by mshockwave in "GCC 16 has been released"

mshockwave — Thu, 30 Apr 2026 16:03:37 +0000

> Does gcc use LLVM anywhere under the hood

New comment by mshockwave in "The RISE RISC-V Runners: free, native RISC-V CI on GitHub"

mshockwave — Mon, 30 Mar 2026 00:09:32 +0000

One thing I observed is that RVV code is usually slower in QEMU

New comment by mshockwave in "Emacs internals: Tagged pointers vs. C++ std:variant and LLVM (Part 3)"

mshockwave — Thu, 12 Mar 2026 18:58:30 +0000

LLVM now has another way to implement RTTI using the `CastInfo` trait instead of `classof`: https://llvm.org/doxygen/structllvm_1_1CastInfo.html

But it's really just an implementation difference, the idea is still to have a lightweight RTTI.

New comment by mshockwave in "We tasked Opus 4.6 using agent teams to build a C Compiler"

mshockwave — Fri, 06 Feb 2026 17:05:34 +0000

how did it do regalloc before instruction selection? How do you select the correct register class without knowing which instruction you're gonna use?

RISC-V Vector Primer

mshockwave — Fri, 06 Feb 2026 16:55:00 +0000

Article URL: https://github.com/simplex-micro/riscv-vector-primer

Comments URL: https://news.ycombinator.com/item?id=46915205

Points: 4

# Comments: 0

New comment by mshockwave in "Banned C++ features in Chromium"

mshockwave — Sat, 24 Jan 2026 18:49:24 +0000

> I don’t know many good reasons for extrusive linked lists

for one, its iterator won't be invalidated

New comment by mshockwave in "Helion: A high-level DSL for performant and portable ML kernels"

mshockwave — Fri, 07 Nov 2025 17:48:17 +0000

Is it normal to spend 10minutes on tuning nowadays? Do we need to spend another 10 minutes upon changing the code?

New comment by mshockwave in "Swift on FreeBSD Preview"

mshockwave — Thu, 06 Nov 2025 18:57:02 +0000

It's likely that Swift compiler is using LLVM LIT (https://llvm.org/docs/CommandGuide/lit.html), which is implemented in python, as the test driver

Machine Scheduler in LLVM – Part II

mshockwave — Sun, 02 Nov 2025 06:13:07 +0000

Article URL: https://myhsu.xyz/llvm-machine-scheduler-2/

Comments URL: https://news.ycombinator.com/item?id=45788167

Points: 31

# Comments: 0