Hacker News: petrohi

DBOS

petrohi — Tue, 12 Mar 2024 23:27:17 +0000

Article URL: https://en.wikipedia.org/wiki/DBOS

Comments URL: https://news.ycombinator.com/item?id=39686143

Points: 17

# Comments: 0

New comment by petrohi in "The Soviet 1801VM2 LSI-11 Processor (2021)"

petrohi — Wed, 31 Jan 2024 01:55:40 +0000

I remember using Soviet-made VAX clone from СМ ЭВМ series:

https://en.m.wikipedia.org/wiki/SM_EVM

New comment by petrohi in "PiDP-11"

petrohi — Tue, 28 Nov 2023 16:55:48 +0000

I want to mention another awesome project, which implements PDP-11 on FPGA and can be used with PiDP-11 panel. (PiDP-11 by default uses software emulator running on Raspberry Pi.)

https://pdp2011.sytse.net/wordpress/

New comment by petrohi in "FPGAs and the renaissance of retro hardware"

petrohi — Mon, 27 Nov 2023 17:41:01 +0000

Not the parent poster, but my experience may be relevant.

My background is exclusively in software engineering and computer science. I started by reading “Digital Design and Computer Architecture”. There’s new RISC-V edition https://a.co/d/imzGBK5 as well as freely available ARM edition https://dl.acm.org/doi/book/10.5555/2815529. The book starts from Boolean logic and transistor technology and goes all the way to assembly programming with everything in between. Most importantly gives great introduction to HDLs. Next I played with a bunch of hardware projects specifically targeting inexpensive Arty-A7 board to get comfortable with FPGA tooling.

I can attest to the parent saying that this is sufficiently different from software engineering I do at my day job and therefore feels a lot more like hobby. Especially if you also foray into wire-wrap prototyping, PCB design and assembly. Finding and fixing analog "bugs" is so much fun!

New comment by petrohi in "Programming on Parallel Machines; GPU, Multicore, Clusters and More"

petrohi — Mon, 20 Nov 2023 06:01:22 +0000

I started by reading “Digital Design and Computer Architecture”. There’s new RISC-V edition https://a.co/d/imzGBK5. The book starts from Boolean logic and transistor technology and goes all the way to assembly programming with everything in between. Most importantly gives great introduction to HDLs. Next I played with a bunch of hardware projects specifically targeting inexpensive Arty-A7 board to get comfortable with FPGA tooling.

Modular launches unified inference framework and new programming language for AI

petrohi — Tue, 02 May 2023 17:06:36 +0000

Article URL: https://www.modular.com/blog/a-unified-extensible-platform-to-superpower-your-ai

Comments URL: https://news.ycombinator.com/item?id=35790779

Points: 6

# Comments: 0

Thousands of conductance levels in memristors integrated on CMOS

petrohi — Fri, 31 Mar 2023 01:22:51 +0000

Article URL: https://www.nature.com/articles/s41586-023-05759-5

Comments URL: https://news.ycombinator.com/item?id=35381169

Points: 3

# Comments: 0

New comment by petrohi in "Wolfenstein 3D with a CGA Renderer"

petrohi — Sun, 22 Jan 2023 21:39:45 +0000

It has TTL RGBI and composite NTSC outputs. The latter is actually very interesting in that it can produce 16-color images using color smearing effect on NTSC TV. Many games from the period used this to achieve more colorful graphics at the expense of dropping to 160x200 resolution. OP port of Wolf3d is also supporting this mode.

I am working on FPGA-based converter to be able to show RGBI and composite CGA on modern VGA screens.

New comment by petrohi in "Wolfenstein 3D with a CGA Renderer"

petrohi — Sun, 22 Jan 2023 21:17:01 +0000

Yes, specifically IBM PCjr-ish clone. Compared to IBM PC 5150 it has 2x slower access to the first 96K of RAM due to “integrated” nature of its non-standard take on CGA. But, the rest of RAM is actually faster than IBM PC because it is a modern retro computing extension card made with fast SRAM.

New comment by petrohi in "Wolfenstein 3D with a CGA Renderer"

petrohi — Sun, 22 Jan 2023 17:29:48 +0000

Tried it on 4.7MHz 8088. Looks great but too slow to enjoy the gameplay.

Getting Tensil to run ResNet at 300 FPS on ZCU104

petrohi — Wed, 03 Aug 2022 05:30:46 +0000

Article URL: https://k155la3.blog/2022/07/29/getting-tensil-to-run-resnet-at-300-fps-on-zcu104/

Comments URL: https://news.ycombinator.com/item?id=32327976

Points: 1

# Comments: 0

Getting ResNet to 300 FPS on ZCU104

petrohi — Fri, 29 Jul 2022 14:47:59 +0000

Article URL: https://k155la3.blog/2022/07/29/getting-resnet-to-300-fps-on-zcu104/

Comments URL: https://news.ycombinator.com/item?id=32277636

Points: 1

# Comments: 0

New comment by petrohi in "Show HN: Speech Controlled Robot on FPGA"

petrohi — Mon, 11 Jul 2022 17:34:31 +0000

This two-part blog explains step by step how to build a robot starting from training the ML model, using FPGA for hardware acceleration, writing an embedded C program and finally assembling everything on the chassis.

Show HN: Speech Controlled Robot on FPGA

petrohi — Mon, 11 Jul 2022 17:08:10 +0000

Article URL: https://k155la3.blog/2022/06/26/building-speech-controlled-robot-with-tensil-and-arty-a7-part1/

Comments URL: https://news.ycombinator.com/item?id=32058785

Points: 3

# Comments: 1

New comment by petrohi in "VeriGPU: GPU in Verilog loosely based on RISC-V ISA"

petrohi — Sat, 23 Apr 2022 19:35:18 +0000

We work on an open source tensor processing unit at https://tensil.ai. It is not RISC-V based since only a handful of very simple instructions is needed for expressing data flows typical in ML.

Show HN: YOLO v4 Tiny with Tensil on Ultra96 FPGA Board

petrohi — Sat, 09 Apr 2022 16:47:44 +0000

Article URL: https://k155la3.blog/2022/04/04/tensil-tutorial-for-yolo-v4-tiny-on-ultra96-v2/

Comments URL: https://news.ycombinator.com/item?id=30969598

Points: 8

# Comments: 0

New comment by petrohi in "Launch HN: Tensil (YC S19) – Open-Source ML Accelerators"

petrohi — Sun, 13 Mar 2022 06:23:23 +0000

Something like the Alveo PCIe card has onboard HBM/DDR4 memory large enough for Tensil DRAM pools, so this would be similar to how GPU operates but could also reach to host memory via PICe if needed. Embedded applications with Zynq 7 and UltraScale+ have ARM processors on the same chip with FPGA and (usually) DDR as separate chips on one PCB. In this case, Tensil DRAM pools are just contiguous memory blocks in the memory shared with the CPU. We will be publishing documentation on the compiler design soon--stay tuned!

New comment by petrohi in "Launch HN: Tensil (YC S19) – Open-Source ML Accelerators"

petrohi — Sun, 13 Mar 2022 05:24:19 +0000

Great questions! With Tensil, all computations are performed on the FPGA. In addition to matrix multiplication Tensil supports SIMD instruction with various operations. The ML activations, average and maximum pooling, normalization, and image resizing use SIMD instruction. Some ML operations, such as padding, are achieved by changing the memory layout. Tensil uses DRAM0 and DRAM1 memory pools (usually in DDR memory) to interact with the host to read model inputs and weights and write outputs. It also uses these pools to offload intermediate results between layers and between tiles within a layer when FPGA does not have sufficient BRAM, which is common on lower-end devices. Tensil compiler takes care of finding the most efficient memory scheduling for given on-FPGA memory size.

New comment by petrohi in "Microcontroller VGA Interface Projects"

petrohi — Sat, 06 Nov 2021 06:11:59 +0000

It’s possible to form monochrome VGA signal with an SPI, which is commonly available in microcontrollers.

I did little write-up on how to do it efficiently (DMA etc) on PIC32: https://hackaday.io/project/173682-color-ascii-terminal/log/...

New comment by petrohi in "Programming PIC32 Microcontroller with Rust"

petrohi — Sun, 10 Oct 2021 17:53:37 +0000

Very glad to see Rust on PIC32! This microcontroller is one of the very few that is still made in DIP package making it ideal for breadboardind and easy through-hole soldering, and by far most powerful, making it ideal choice for interesting projects.