Hacker News: random__duck

New comment by random__duck in "OpenTPU – An open-source AI accelerator, developed by AI"

random__duck — Tue, 06 Oct 2026 18:10:11 +0000

Opened the RTL, looked at the floating point math, learned that apparently you don't need correct floating point operations for LLMs, closed the page.

New comment by random__duck in "How OpenAI Used Its Own LLMs to Design Its Jalapeño Chip"

random__duck — Mon, 21 Sep 2026 05:31:36 +0000

Finally, thanks for stating the obvious! I was starting to wonder if I was not going insane.

A team of senior elite chip designers builds something they already know how to build and everyone goes "wow AI be so powerful".

New comment by random__duck in "Open source FPGA: the next frontier is silicon"

random__duck — Thu, 10 Sep 2026 02:39:06 +0000

Open source FPGA silicon in the wild, and it works.

Open source FPGA: the next frontier is silicon

random__duck — Thu, 10 Sep 2026 02:39:06 +0000

Article URL: https://www.reddit.com/r/FPGA/comments/1wbrrgi/open_source_fpga_the_next_frontier_is_silicon/

Comments URL: https://news.ycombinator.com/item?id=49637697

Points: 2

# Comments: 1

New comment by random__duck in "RISC-V: They Should Have Known Better"

random__duck — Fri, 14 Aug 2026 22:05:26 +0000

> slighly crazy

What a lovely euphemism.

Signed: someone slightly crazy.

New comment by random__duck in "RISC-V: They Should Have Known Better"

random__duck — Fri, 14 Aug 2026 21:44:01 +0000

"This time its different".

New comment by random__duck in "RISC-V: They Should Have Known Better"

random__duck — Fri, 14 Aug 2026 17:09:19 +0000

I wonder if they will be inviting him to the next RISC-V design committee meeting.

New comment by random__duck in "Apple is getting this wrong"

random__duck — Tue, 04 Aug 2026 06:30:30 +0000

Spot on, while reading this post I couldn't help be wonder "but what about the prototypes"?

New comment by random__duck in "Designing an Ethernet Switch ASIC"

random__duck — Sat, 25 Jul 2026 13:04:26 +0000

No AI was used either for the project itself or for the post. I encourage you to look at the code and the git history.

New comment by random__duck in "Designing an Ethernet Switch ASIC"

random__duck — Sat, 25 Jul 2026 00:02:34 +0000

As the designer of "an ethernet connected beacon that counts and never overflows until the heat death of the universe" (https://talesonthewire.com/projects/until_heat_death_do_us_p...) I believe you have found the perfect audience for a memeish hardware project. So don't expect anything but my upmost support. :)

I detailed the roadmap for custom ASIC design a bit here: https://talesonthewire.com/projects/two_weeks_until_tapeout/... and joining the Tiny Tapeout discord community is a great place to reach out for help.

New comment by random__duck in "Designing an Ethernet Switch ASIC"

random__duck — Fri, 24 Jul 2026 23:27:33 +0000

No AI was used either for the project itself or for the post.

New comment by random__duck in "Designing an Ethernet Switch ASIC"

random__duck — Fri, 24 Jul 2026 22:27:16 +0000

Nice, thanks for posting the link. For the people unfamiliar with the Tiny Tapeout program: everyone that gets a copy of the Tiny Tapeout chip will be getting a copy of all the ASICs on the shuttle.

New comment by random__duck in "Designing an Ethernet Switch ASIC"

random__duck — Fri, 24 Jul 2026 22:24:23 +0000

True, I went over the EDA stack a bit in a previous article here: https://talesonthewire.com/projects/blake2s_hashing_accelera...

This used the librelane classic flow, so it's a lot of verilator, yosys, openroad, opensta, magic and klayout. :)

New comment by random__duck in "Designing an Ethernet Switch ASIC"

random__duck — Fri, 24 Jul 2026 21:53:31 +0000

You can join multiple Tiny Tapeout tiles (grid squares) together to form bigger projects, which is what I did here. It's actually one of the bigger 4 grid projects.

Also how much you can fit really depends on the node the shuttle is targeting. So I was in luck that this was on Global Foundries 180nm as you can cram in a lot for flip-flops onto a single tile compared with Skywater 130nm. On the other hand the gates are much slower than on Skywater 130nm.

Hopefully both programs will be around for a while, so if you are still interested when you have more time you can join the shuttle then.

New comment by random__duck in "Designing an Ethernet Switch ASIC"

random__duck — Fri, 24 Jul 2026 21:36:12 +0000

Sounds like they could have used you on that team. Bad luck, but it at least you can walk away proud knowing it was not an issue with your technical skills. :)