Hacker News: rosscomputerguy

New comment by rosscomputerguy in "Aegis – open-source FPGA silicon"

rosscomputerguy — Tue, 07 Apr 2026 04:58:13 +0000

Please vote in this poll: https://github.com/MidstallSoftware/aegis/discussions/11

New comment by rosscomputerguy in "Aegis – open-source FPGA silicon"

rosscomputerguy — Tue, 07 Apr 2026 04:58:08 +0000

Please vote in this poll: https://github.com/MidstallSoftware/aegis/discussions/11

New comment by rosscomputerguy in "Aegis – open-source FPGA silicon"

rosscomputerguy — Sun, 05 Apr 2026 21:43:43 +0000

I've definitely had a thought about doing a hard core RISC-V SoC on a dev board.

New comment by rosscomputerguy in "Aegis – open-source FPGA silicon"

rosscomputerguy — Sun, 05 Apr 2026 21:08:36 +0000

Yep, Aegis's Terra 1 is designed to be "good enough" for the first generation. I do plan on expanding the Terra family of FPGA's if there's enough interest. I do want to work my way up to 100k LUT's.

New comment by rosscomputerguy in "Aegis – open-source FPGA silicon"

rosscomputerguy — Sun, 05 Apr 2026 21:07:27 +0000

You can already port over a RISC-V SoC to Aegis. I have not tested that yet but it is something I really want to do.

New comment by rosscomputerguy in "Aegis – open-source FPGA silicon"

rosscomputerguy — Sun, 05 Apr 2026 14:51:03 +0000

Yeah, I did see there's been attempts but none really satisfied what I wanted out of it. I do know of FABulous and it seems good but not quite what I wanted. You can see that aside from yosys and nextpnr, it is quite self contained and even provides a very easy way of defining new silicon with Nix.

I know that IO is really the 2nd thing which sells FPGA's. I did design a basic serdes hardware that should just work for this first generation. I do want to do DDR IO cells in the future.

New comment by rosscomputerguy in "Aegis – open-source FPGA silicon"

rosscomputerguy — Sun, 05 Apr 2026 14:47:19 +0000

Thanks for the suggestion on the DSP. Maybe I'll add new DSP tiles that are reconfigurable and keep the config based DSP tiles. I designed Aegis's Terra 1 to be a "good enough first gen" so that's why things are the way they are. I didn't want to over commit on the design for a first generation.

Aegis – open-source FPGA silicon

rosscomputerguy — Sun, 05 Apr 2026 05:50:04 +0000

Article URL: https://github.com/MidstallSoftware/aegis

Comments URL: https://news.ycombinator.com/item?id=47646472

Points: 153

# Comments: 43

Ziptools – Modern zip and unzip replacements

rosscomputerguy — Sat, 23 Aug 2025 01:00:03 +0000

Article URL: https://github.com/RossComputerGuy/ziptools

Comments URL: https://news.ycombinator.com/item?id=44991895

Points: 2

# Comments: 0

SELinux on NixOS

rosscomputerguy — Sun, 06 Apr 2025 05:49:32 +0000

Article URL: https://tristanxr.com/post/selinux-on-nixos/

Comments URL: https://news.ycombinator.com/item?id=43599238

Points: 16

# Comments: 2