Hacker News: sdbbp

New comment by sdbbp in "The secret medieval tunnels that we still don't understand"

sdbbp — Wed, 21 Jan 2026 00:01:12 +0000

Was there a populist (home) mining fad? People got excited about digging for possible resources and dug crude exploratory tunnels?

New comment by sdbbp in "Milei Wins Mandate for Free-Market Revolution in Argentina's Election"

sdbbp — Mon, 27 Oct 2025 02:33:47 +0000

Try some peñas folklóricas.

New comment by sdbbp in "I'm the CTO of Palantir. Today I Join the Army"

sdbbp — Fri, 13 Jun 2025 18:14:14 +0000

The people in that list all sound sketchy. Where are the "good guys"?

New comment by sdbbp in "XiangShan – Open-source high performance RISC-V processor"

sdbbp — Fri, 03 Jan 2025 05:17:02 +0000

That's the HDL, and not the inherent design complexity.

New comment by sdbbp in "Meta Bans Accounts Tracking Private Jets for Zuckerberg, Musk"

sdbbp — Tue, 22 Oct 2024 22:52:52 +0000

Fediverse: https://mastodon.social/@elonjet

New comment by sdbbp in "Memory Consistency Models: A Tutorial"

sdbbp — Tue, 14 May 2024 05:56:57 +0000

See also https://www.cs.cmu.edu/afs/cs/academic/class/15740-f18/www/p... and Gharachorloo's thesis paper.

New comment by sdbbp in "Memory Consistency Models: A Tutorial"

sdbbp — Tue, 14 May 2024 05:51:02 +0000

Probably "A Primer on Memory Consistency and Cache Coherence"

New comment by sdbbp in "Temporal Fuzzing I: Memory Models (2021)"

sdbbp — Thu, 09 May 2024 04:09:33 +0000

It would be interesting to see this interact with the lower-level ISA memory model work in diy, litmus, etc. Could you validate your ISA memory models against the generated litmus tests in https://www.cl.cam.ac.uk/~pes20/ppc-supplemental/test6.pdf, https://github.com/litmus-tests/litmus-tests-riscv?

New comment by sdbbp in "Confessions of a Country Parson"

sdbbp — Sun, 14 Jan 2024 23:10:07 +0000

If you like following historical diaries, @samuelpepys is hard to beat.

New comment by sdbbp in "The Ugly Truth Behind “We Buy Ugly Houses”"

sdbbp — Fri, 12 May 2023 07:39:34 +0000

I used to go to Sundown yearly, a long time ago. I'm not saying it's great, but I did learn to ski there.

https://www.sundownmtn.com/the-mountain/snow-report-trail-ma...

New comment by sdbbp in "The Pretty Good House"

sdbbp — Tue, 17 Jan 2023 07:20:43 +0000

Consider a separate architect to design the place with you. They can help find a general contractor to be the "builder", but also serve as an owner's representative to oversee construction intent. They want the design done well, as well.

New comment by sdbbp in "RISC-V J extension – Instructions for JITs"

sdbbp — Sat, 12 Mar 2022 02:18:22 +0000

This organization of functionality is intentional. It provides support for code modification orthogonal to instruction cache coherency support. The range of types of implementations of RISC-V is broad enough that imposing instruction cache coherency on all of them wouldn't be optimal. The I/D consistency proposal provides SW control now, while not requiring particular implementations.

Particular RISC-V Platform specs may end up requiring I/D coherency, like Arm is recommending in SBSA Level 6, but that's left for later, if ever.

New comment by sdbbp in "New SiFive RISC-V core P650 with 40% IPC increase"

sdbbp — Fri, 03 Dec 2021 06:52:03 +0000

This in-depth presentation is good: https://www.youtube.com/watch?v=oTaOd8qr53U

New comment by sdbbp in "Ask HN: Who is hiring? (September 2021)"

sdbbp — Wed, 01 Sep 2021 20:10:03 +0000

We are a well-funded start-up, founded by seasoned industry veterans, that is developing a family of best-in-class, high-performance RISC-V CPU cores focused on a chiplet form factor. Start working now in the growing community around the open RISC-V instruction set architecture.

Software Engineer: Software development and performance optimization for high-performance embedded and server platforms. Various roles available. Work on compilers, language runtimes, operating system internals (Linux), device drivers, hypervisor, boot and runtime firmware, much of it open source. swjobs@ventanamicro.com

New comment by sdbbp in "Back That ‘S’ Up: Moving to RISC-V’s Supervisor Mode"

sdbbp — Tue, 01 Dec 2020 21:23:13 +0000

This was clarified this year. I think the author's context is moving from Bare to one of the Sv modes.

https://github.com/riscv/riscv-isa-manual/commit/866326d938c...

New comment by sdbbp in "Ask HN: Who is hiring? (December 2020)"

sdbbp — Tue, 01 Dec 2020 20:22:03 +0000

Ventana Micro Systems is a well-funded, early stage start-up, founded by seasoned industry veterans, that is developing a family of best-in-class, high-performance RISC-V CPU cores and compute subsystems. Start working now in the growing community around the open RISC-V instruction set architecture.

Candidates with significant experience in the following areas requested.

Software Engineer: Software development and performance optimization for high-performance embedded and server platforms. Various roles available. Work on language runtimes, operating system internals (Linux), device drivers, hypervisor, boot and runtime firmware. swjobs@ventanamicro.com

Design Verification Engineer: Functional design verification of CPU cores and related components. Focus on architecture and / or microarchitecture. Infrastructure, testplans, testbenches, test generation, coverage and debug. Simulation and formal. Work primarily in SystemVerilog, Python, C, and assembly. jobs@ventanamicro.com

New comment by sdbbp in "Leslie Lamport: Video course on TLA+"

sdbbp — Tue, 21 Mar 2017 15:13:00 +0000

In my experience, writing a formal specification _once_ in TLA+ has shaped my mindset around architecture, implementation, and verification of distributed systems for the last 19 years. It's easier to provide feedback on most informal architecture specifications. It is easier to implement to a specification so as to have a higher confidence of compliance. It is easier to consider the state space of an architecture (distributed system) when in a testing/verification role.

New comment by sdbbp in "Sometimes the bug isn't in your code, it's in the CPU"

sdbbp — Tue, 06 Mar 2012 05:30:49 +0000

There's little open development, so there's little incentive to write up public articles. You could try something like Bob Colwell's "The Pentium Chronicles".

New comment by sdbbp in "Sometimes the bug isn't in your code, it's in the CPU"

sdbbp — Tue, 06 Mar 2012 05:13:02 +0000

The amount of effort spent on what is generally called "functional verification" is much higher for hardware than for software. Also, the specifications tend to be clearer and the source code size is smaller than you might imagine.

New comment by sdbbp in "7% of Americans Subscribe to Netflix, Now Larger than any Cable Company"

sdbbp — Tue, 26 Apr 2011 01:46:14 +0000

I use greencine.com