https://www.carwow.co.uk/blog/carwow-quarter-mile-400-metre-...

https://en.wikipedia.org/wiki/List_of_N%C3%BCrburgring_Nords...

Macromedia Flash taught me this in the early 2000s...

This percentage directly determines the influence on SP500 index funds holders (SPY, VOO, etc.).

The outcome could have been:

1. not included (0%)

2. included, weight by free float (0.3%) --- 54th in the list between $AXP and $MCD

3. included, weight by free float x 3 (0.9%) --- 19th in the list between $ORCL and $JNJ

4. included, weight by market cap (1.75 trillion / 67 trillion = 2.6%) --- 8th in the list between $AVGO and $META

https://www.slickcharts.com/sp500

#2 is _much_ closer to #1 than #3 (let alone #4), meaning that had an exemption been made to allow SpaceX in, given the rest of the existing rules, at least the impact to ETF holders would not be outblown. The same could not be said for NASDAQ , which was the main source of all the debate.

Brought up in a low-trust env and this became habitual.

As for autonomy, Waymos have LIDARs which at least provides more redundancy.

I see these as different design tradeoffs so no judgment implied.

This is precisely what leads to the "forgot to multiply 2pi or 1/(2pi)" problem in the EE / signal processing domain where you FFT and s-/fourier-transform back and forth. Heck, I can never remember which convention any particular library / package decides to adopt (esp. mathematica vs. matlab which IIRC caused tons of confusion and headache during my undergrad).

Early 2000s RTS games (Starcraft 1, Warcraft 3, CnC franchise) continue to amaze me in how well their seemingly comical "game physics" model the intrinsic dynamics of real world conflicts, almost prophetically.

The tradeoff with these unified LPDDR machines is compute and memory throughput. You'll have to live with the ~50 token/sec rate, and compact your prefix aggressively. That said, I'd take the effortless local model capability over outright speed any day.

Hope the popularity of these machines could prompt future models to offer perfect size fits: 80 GiB quantized on 128 GiB box, 480 GiB quantized on 512 GiB box, etc.

https://awsdocs-neuron.readthedocs-hosted.com/en/latest/abou...

https://awsdocs-neuron.readthedocs-hosted.com/en/latest/nki/...

Eight NeuronCore-v4 cores that collectively deliver:

    2,517 MXFP8/MXFP4 TFLOPS
    671 BF16/FP16/TF32 TFLOPS
    2,517 FP16/BF16/TF32 sparse TFLOPS
    183 FP32 TFLOPS

SRAM: 32 MiB * 8 = 256 MiB (ignoring 2 MiB * 8 = 16 MiB of PSUM which is not really general-purpose nor DMA-able)

Interconnect: 2560 GB/s (I think bidirectional, i.e. Jensen Math™)

----

At 3nm process node the FLOP/s is _way_ lower than competition. Compare to B200 which does 2250 BF16, x2 FP8, x4 FP4. TPU7x does 2307 BF16, x2 FP8 (no native FP4). HBM also lags behind (vs ~192 GiB in 6 stacks for both TPU7x and B200).

The main redeeming qualities seem to be: software-managed SRAM size (double of TPU7x; GPUs have L2 so not directly comparable) and on-paper raw interconnect BW (double of TPU7x and more than B200).

Same logic when NVidia quote the "bidirectional bandwidth" of high speed interconnects to make the numbers look big, instead of the more common BW per direction, forcing everyone else to adopt the same metric in marketing materials.