0. https://www.youtube.com/watch?v=RfukJ6uVHXs

There are also hardware-based efforts, like BoxLambda[0], Agon[1], MEGA65[2], Uzebox[3], F256[4].

0. https://epsilon537.github.io/boxlambda/

1. https://www.thebyteattic.com/p/agon.html

2. https://mega65.org/

3. https://uzebox.org/

4. https://wildbitscomputing.com/

This is an argument for preservation.

i.e. everything should be available via sailing the seas. If something isn't, and you know where to obtain it, do your part.

Many films and records have been lost because nobody cared to do it.

e.g. I'd love to see cycles spent in each mode (machine/supervisor/user). Also how much idle (wfi).

0. https://riscv.org/about/brand-guidelines/

This does not feel like the sort of error somebody going so far as to implement this would make.

Gut feeling is not good. Unfortunate.

2026, we are still dealing with this kinda thing.

It is good that seL4 is now its own organization, fully independent. A tragedy that it was hampered by CSIRO for so many years.

0. https://microkerneldude.org/2022/02/17/a-story-of-betrayal-c...

Shrug. The first RVA23-compliant chips are coming soon.

spacemiT K3 imminent (likely shipping boards this month) and Tenstorrent Ascalon (via Atlantis SoC devboard) this summer. These won't be the fastest CPUs available, but they'll meet the "fast enough" criteria for many uses and users.

Multiple parties including Tenstorrent expect performance parity with the ARM and x86 offerings available at the same time by 2028. Note performance is mainly gated by access to latest fab nodes, which comes with costs that necessitate serious volume. They expect to be there by then.

>But I don’t understand why the industry decided to start over with RISC-V when the compilers and toolchains and chips already existed in power land.

The rationale was documented in the "Instruction Sets Should Be Free: The Case For RISC-V" paper[0].

Note OpenPOWER is mentioned but is not in the comparison. The reason for that is simple: RISC-V predates OpenPOWER. It was an obvious reaction to RISC-V, and they were too late, as RISC-V already had the industry's attention. Furthermore, Open is a lie; payment to IBM is required in practice.

0. https://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-...

0. https://www.youtube.com/watch?v=RfukJ6uVHXs

There's nothing inherently slow about it, anymore than there is anything inherently slow about x86 or ARM.

High performance microarchitecture implementations are definitely possible. Some of them are available for licensing.

At least one of them (Tenstorrent Ascalon) has been tapped out into a chip and will show up in development boards later this year.

I am hopeful as ModRetro's m64 launches, with a FPGA larger than the one in the miSTer, and there's an associated influx of developers looking at the platform, we'll see renewed energy directed towards understanding the N64.

It replaced a very unreliable, problematic setup somebody else had set up in the past, which was based on an android phone.

Once I got the sim900-derived device from aliexpress, I moved the sim over and had it working in less than an hour. Polished the code and its setup during the first few days of use, and hadn't had to touch it since.

Definitely cheaper, and far more reliable than a complex device running a full android stack.

$20 and full android stack seems a massive waste for this, nevermind unreliable.