Hacker News: trynumber9

New comment by trynumber9 in "Xiaomi: New CPU matches Apple cores single threaded, much faster multithreaded"

trynumber9 — Mon, 24 Aug 2026 20:39:00 +0000

There is a nuance: Xiaomi is not Huawei. They were not sanctioned. This chip is made in Taiwan like all the non-Samsung competition.

New comment by trynumber9 in "Xiaomi: New CPU matches Apple cores single threaded, much faster multithreaded"

trynumber9 — Mon, 24 Aug 2026 19:02:19 +0000

In this case it's more that multiple companies (Apple, Qualcomm, MediaTek and now Xiaomi) have used the same process (N3P) to produce multiple chips with similar performance. Regardless of Moore's Law death that isn't surprising.

New comment by trynumber9 in "Xiaomi: New CPU matches Apple cores single threaded, much faster multithreaded"

trynumber9 — Mon, 24 Aug 2026 16:02:45 +0000

Xiaomi has not been sanctioned like Huawei. So it is made by TSMC on N3P. The Huawei chips, made by SMIC, are so far behind they're not competitive at all with even Xiaomi's first generation chip.

New comment by trynumber9 in "2027 memory capacity is reportedly sold out"

trynumber9 — Fri, 07 Aug 2026 20:17:25 +0000

Memory prices are cyclical. But this is bigger and longer than most cycles.

New comment by trynumber9 in "Why Switzerland has 25 gbit internet and America doesn't"

trynumber9 — Fri, 03 Jul 2026 04:32:18 +0000

I guess they don't bother using Speedtest in Switzerland, as the average speed seems about the same as the US: https://www.speedtest.net/global-index

Must be a sampling bias or something.

New comment by trynumber9 in "Have you restarted your computer this week?"

trynumber9 — Wed, 01 Jul 2026 02:56:59 +0000

AMD's first Athlon chips did not run particularily hot. They needed a fan, just like Williamette chips, but actually used less power than the competition. The difference was they had no internal, on-chip diode. If the heatsink and fan fell off, then the chip could cook itself. The boards had a thermal sensor to initiate shutdown if the fan stopped working. But it's debateable if it would detect it quickly enough if the entire cooler fell off.

In that scenario, shutting it off seems better. But it might roast itself on start up anyway.

New comment by trynumber9 in "IBM debuts sub-1 nanometer chip technology"

trynumber9 — Fri, 26 Jun 2026 02:44:12 +0000

The plan doesn't involve running fabs again. Too expensive. IBM licenses their manufacturing technology (so far to Rapidus in Japan).

New comment by trynumber9 in "Nvidia is proposing a beast of a CPU system for Windows PCs"

trynumber9 — Sun, 07 Jun 2026 02:24:27 +0000

No, it stems from a lineage of Tegra chips that pre-date the M-Series. This chip was called GB10. One of its predecessors, GV10 was shipped in 2018. It was a 256 bit, unified-memory system on a chip with a Volta GPU and 12 ARM Cores. GB10 is a 256 bit, unified-memory system on a chip with a Blackwell GPU and 10+10 ARM cores.

New comment by trynumber9 in "Microsoft builds MacBook Pro rival with NVIDIA-powered Surface Laptop Ultra"

trynumber9 — Mon, 01 Jun 2026 20:16:48 +0000

MediaTek designed X925 + A725 CPU. It's already been benchmarked in the GB10 products. It is not even close. Like 0.75x SPECint 2017 of the M5.

New comment by trynumber9 in "Microsoft builds MacBook Pro rival with NVIDIA-powered Surface Laptop Ultra"

trynumber9 — Mon, 01 Jun 2026 19:02:27 +0000

It's the same configuration as GB10. 20 core MediaTek 3nm part which is competitive with a AMD's 2025 16 core 4nm part with similar power draw.

https://www.servethehome.com/wp-content/uploads/2026/05/cpu2...

New comment by trynumber9 in "It's hard to justify buying a Framework 12"

trynumber9 — Fri, 29 May 2026 16:56:52 +0000

What's the real cause of them being unable to price competitively?

Is it DRAM, NAND flash storage, SoC cost, simply scale?

New comment by trynumber9 in "SimCity 3k in 4k (2025)"

trynumber9 — Wed, 27 May 2026 18:04:11 +0000

I must also admit to preferring Sim City 3000 over 4. I don't know if I can handle a 4K user interface without a magnifier, however.

New comment by trynumber9 in "College students drown out AI-praising commencement speeches with boos"

trynumber9 — Wed, 20 May 2026 15:33:39 +0000

I suspect general attitude to AI will split along those who had to apply for jobs in the post-AI world of automatic resume generation and filtering and those who didn't.

New comment by trynumber9 in "New Lifetime Plex Pass Pricing"

trynumber9 — Tue, 19 May 2026 14:54:40 +0000

There's little reason at this price. I run both, Plex for people who are already used to it, and Jellyfin for myself and anyone new. At around ~$100 I think the Plex experience was better enough to justify it, personally.

New comment by trynumber9 in "NetHack 5.0.0"

trynumber9 — Sat, 02 May 2026 23:13:25 +0000

Nethack embeds Lua 5.4.8, so you don't need it installed from a distribution's package manager. As long as your system can build C99* it can build Lua. And given that Nethack 5.0.0 is C99, this dependency is not reducing portability any further.

* Lua has a LUA_USE_C89 flag so it may be more portable than Nethack 5.0.0 at this point.

New comment by trynumber9 in "Windows Server 2025 Runs Better on ARM"

trynumber9 — Wed, 22 Apr 2026 15:34:43 +0000

@jasoneckert For the sake of science, can you disable your e cores and try this test again?

New comment by trynumber9 in "Analyzing Geekbench 6 under Intel's BOT"

trynumber9 — Wed, 01 Apr 2026 04:43:59 +0000

Question: do those vectorize code as in the example here? I was of the understanding they performed a more limited subset of optimizations.

New comment by trynumber9 in "Linux is an interpreter"

trynumber9 — Sun, 29 Mar 2026 05:35:48 +0000

Some instructions are microcoded but others take the fast path and avoid the microcode sequencer. Can't patch the latter in microcode RAM.

New comment by trynumber9 in "AMD's Ryzen 9 9950X3D2 Dual Edition crams 208MB of cache into a single chip"

trynumber9 — Sat, 28 Mar 2026 21:42:56 +0000

It does not. For any of the dual CCD parts AMD has ever released for consumers. Even Strix Halo which has higher bandwidth, lower latency interconnect doesn't make a single L3 across CCDs.

It'll probably only happen when they have a singular, large die filled with cache upon which both CCDs are stacked.

Run this test if you're curious: https://github.com/ChipsandCheese/MemoryLatencyTest

New comment by trynumber9 in "AMD's Ryzen 9 9950X3D2 Dual Edition crams 208MB of cache into a single chip"

trynumber9 — Sat, 28 Mar 2026 04:48:16 +0000

Per compute die it functions as one 96M L3 with uniform latency. It is 4 cycles more latency than the configuration with smaller 32M L3. But there are two compute dies, each with their own L3. And like the 9950X coherency between these two L3 is maintained over global memory interconnect to the third (IO) die.