<rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Hacker News: ulrichxtan</title><link>https://news.ycombinator.com/user?id=ulrichxtan</link><description>Hacker News RSS</description><docs>https://hnrss.org/</docs><generator>hnrss v2.1.1</generator><lastBuildDate>Mon, 08 Jun 2026 15:56:40 +0000</lastBuildDate><atom:link href="https://hnrss.org/user?id=ulrichxtan" rel="self" type="application/rss+xml"></atom:link><item><title><![CDATA[New comment by ulrichxtan in "WOS: a Rust ARM64 kernel from scratch with MMU and GICv2 working"]]></title><description><![CDATA[
<p>To my knowledge, there’s nothing on RISC‑V that’s equivalent to WOS in the “from‑scratch, bare‑metal bring‑up” sense (MMU, interrupt controller, exception levels, etc.).<p>However, there are several advanced Rust projects on RISC‑V, but they focus on higher‑level OS features rather than the low‑level hardware bring‑up. For instance:<p>- rCore — teaching OS in Rust
<a href="https://github.com/rcore-os/rcore" rel="nofollow">https://github.com/rcore-os/rcore</a>  
- TockOS — Rust microkernel with RISC‑V support
<a href="https://github.com/tock/tock" rel="nofollow">https://github.com/tock/tock</a>  
- RustSBI — SBI runtime (not an OS)
<a href="https://github.com/rustsbi/rustsbi" rel="nofollow">https://github.com/rustsbi/rustsbi</a>  
- xv6-riscv-rust — Rust port of xv6
<a href="https://github.com/garentyler/xv6-riscv" rel="nofollow">https://github.com/garentyler/xv6-riscv</a><p>These projects are more “advanced” in terms of OS features (processes, syscalls, userland), but none of them do the full low‑level bring‑up that WOS does on ARM64 (not to what I know of).<p>So the space is still wide open if someone wants to do a true from‑scratch RISC‑V kernel in Rust.</p>
]]></description><pubDate>Mon, 08 Jun 2026 15:53:52 +0000</pubDate><link>https://news.ycombinator.com/item?id=48446985</link><dc:creator>ulrichxtan</dc:creator><comments>https://news.ycombinator.com/item?id=48446985</comments><guid isPermaLink="false">https://news.ycombinator.com/item?id=48446985</guid></item><item><title><![CDATA[WOS: a Rust ARM64 kernel from scratch with MMU and GICv2 working]]></title><description><![CDATA[
<p>Article URL: <a href="https://github.com/jietra/wos">https://github.com/jietra/wos</a></p>
<p>Comments URL: <a href="https://news.ycombinator.com/item?id=48444020">https://news.ycombinator.com/item?id=48444020</a></p>
<p>Points: 1</p>
<p># Comments: 2</p>
]]></description><pubDate>Mon, 08 Jun 2026 11:32:09 +0000</pubDate><link>https://github.com/jietra/wos</link><dc:creator>ulrichxtan</dc:creator><comments>https://news.ycombinator.com/item?id=48444020</comments><guid isPermaLink="false">https://news.ycombinator.com/item?id=48444020</guid></item></channel></rss>