<rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Hacker News: zir_blazer</title><link>https://news.ycombinator.com/user?id=zir_blazer</link><description>Hacker News RSS</description><docs>https://hnrss.org/</docs><generator>hnrss v2.1.1</generator><lastBuildDate>Mon, 17 Aug 2026 03:57:44 +0000</lastBuildDate><atom:link href="https://hnrss.org/user?id=zir_blazer" rel="self" type="application/rss+xml"></atom:link><item><title><![CDATA[New comment by zir_blazer in "SIMD in the 90s: Programming Intel's Pentium MMX"]]></title><description><![CDATA[
<p>>> I believe that only the first Pentium 3 core, Katmai, did this.<p>> No, all Pentium 3s as well as the Pentium M. Pentium 4 notably didn't suffer from it, but it of course had many, many, MANY other performance issues.<p>I had to google a bit to confirm this, and seems like I'm not the only one that understood it the way I did:<p><a href="https://www.vogons.org/viewtopic.php?p=1360606#p1360606" rel="nofollow">https://www.vogons.org/viewtopic.php?p=1360606#p1360606</a><p><a href="https://www.vogons.org/viewtopic.php?p=1360620#p1360620" rel="nofollow">https://www.vogons.org/viewtopic.php?p=1360620#p1360620</a><p>Basically, the info I knew was that Katmai had 128 Bits SSE registers but processed it as 2x64 Bits. That info is well reference pretty much everywhere. What is NOT explicitly mentioned is whenever Coppermine/Tualatin maintained that arrangement or had 128 Bits compute units for SSE, so the wording always made Katmai to look like an exception, as if everything else was 128 Bits.</p>
]]></description><pubDate>Mon, 17 Aug 2026 01:15:39 +0000</pubDate><link>https://news.ycombinator.com/item?id=49325544</link><dc:creator>zir_blazer</dc:creator><comments>https://news.ycombinator.com/item?id=49325544</comments><guid isPermaLink="false">https://news.ycombinator.com/item?id=49325544</guid></item><item><title><![CDATA[New comment by zir_blazer in "SIMD in the 90s: Programming Intel's Pentium MMX"]]></title><description><![CDATA[
<p>> Additionally, some CPUs at the time only had a 64-bit data path and had to split SSE2 ops, but because of their 4-1-1 decode template, could only decode one such instruction per cycle.<p>I believe that only the first Pentium 3 core, Katmai, did this.<p>> This caused some confusion with the 64-bit version of Windows since Microsoft tried to say that x87/MMX shouldn't be used in long mode, but after queries from video processing companies had to document that the x87/MMX registers were enabled and context switched for user mode code.<p>I have some faint memories of hearing somewhere that Long Mode didn't support x87. I wonder if it is related to this early info you mention and it being Microsoft specific.</p>
]]></description><pubDate>Sun, 16 Aug 2026 21:55:16 +0000</pubDate><link>https://news.ycombinator.com/item?id=49324098</link><dc:creator>zir_blazer</dc:creator><comments>https://news.ycombinator.com/item?id=49324098</comments><guid isPermaLink="false">https://news.ycombinator.com/item?id=49324098</guid></item><item><title><![CDATA[New comment by zir_blazer in "The First Open-Source Firmware Released for Modern AMD Ryzen AM5 Platform"]]></title><description><![CDATA[
<p>Currently it should work only with Phoenix based APUs (8700G and 8600G, the non-IGP 8700F and 8400F, and whatever other GE or PRO versions of those). It was already mentioned elsewhere that Phoenix2 8300G and 8500G does NOT work, so expect the doc to be fixed ASAP.</p>
]]></description><pubDate>Fri, 31 Jul 2026 18:39:33 +0000</pubDate><link>https://news.ycombinator.com/item?id=49127027</link><dc:creator>zir_blazer</dc:creator><comments>https://news.ycombinator.com/item?id=49127027</comments><guid isPermaLink="false">https://news.ycombinator.com/item?id=49127027</guid></item><item><title><![CDATA[The First Open-Source Firmware Released for Modern AMD Ryzen AM5 Platform]]></title><description><![CDATA[
<p>Article URL: <a href="https://www.phoronix.com/news/OSS-Firmware-MSI-B850-P-WIFI">https://www.phoronix.com/news/OSS-Firmware-MSI-B850-P-WIFI</a></p>
<p>Comments URL: <a href="https://news.ycombinator.com/item?id=49127026">https://news.ycombinator.com/item?id=49127026</a></p>
<p>Points: 5</p>
<p># Comments: 1</p>
]]></description><pubDate>Fri, 31 Jul 2026 18:39:33 +0000</pubDate><link>https://www.phoronix.com/news/OSS-Firmware-MSI-B850-P-WIFI</link><dc:creator>zir_blazer</dc:creator><comments>https://news.ycombinator.com/item?id=49127026</comments><guid isPermaLink="false">https://news.ycombinator.com/item?id=49127026</guid></item></channel></rss>